SLVS753C February   2007  – November 2016 TPS40180

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Sensing and Overcurrent Detection
      2. 7.3.2 Hiccup Fault Recovery
      3. 7.3.3 Selecting Current Sense Network Components
      4. 7.3.4 PGOOD Functionality
      5. 7.3.5 Output Overvoltage and Undervoltage Protection
      6. 7.3.6 Overtemperature Protection
      7. 7.3.7 eTRIM™
      8. 7.3.8 Connections Between Controllers for Stacking
      9. 7.3.9 VSH Line in the Multiphase
    4. 7.4 Device Functional Modes
      1. 7.4.1 Tracking
    5. 7.5 Programming
      1. 7.5.1 Programming the Operating Frequency
      2. 7.5.2 Programming the Soft-Start Time
      3. 7.5.3 Using the Device for Clock Master/Slave Operation
      4. 7.5.4 Using the TPS40180 for Voltage Control Loop Master or Slave Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Single Output Synchronous Buck Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Inductor Selection
          2. 8.2.1.2.2 Output Capacitor Selection
          3. 8.2.1.2.3 Input Capacitor Selection
          4. 8.2.1.2.4 MOSFET Selection
          5. 8.2.1.2.5 Peripheral Component Design
            1. 8.2.1.2.5.1  Switching Frequency Setting (RT)
            2. 8.2.1.2.5.2  Output Voltage Setting (FB)
            3. 8.2.1.2.5.3  Current Sensing Network Design (CS+, CS-)
            4. 8.2.1.2.5.4  Overcurrent Protection (ILIM)
            5. 8.2.1.2.5.5  VREG (PVCC)
            6. 8.2.1.2.5.6  BP5
            7. 8.2.1.2.5.7  Phase Select (PSEL)
            8. 8.2.1.2.5.8  VSHARE (VSH)
            9. 8.2.1.2.5.9  Powergood (PGOOD)
            10. 8.2.1.2.5.10 Undervoltage Lockout (UVLO)
            11. 8.2.1.2.5.11 Clock Synchronization (CLKIO)
            12. 8.2.1.2.5.12 Bootstrap Capacitor
            13. 8.2.1.2.5.13 Soft Start (SS)
            14. 8.2.1.2.5.14 Remote Sense
            15. 8.2.1.2.5.15 Feedback Compensator Design
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Simultaneous Tracking With TPS40180 Devices
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 2-Phase Single Output With TPS40180
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Inductor Selection
          2. 8.2.3.2.2 Output Capacitor Selection
          3. 8.2.3.2.3 Input Capacitor Selection
          4. 8.2.3.2.4 Peripheral Component Design
            1. 8.2.3.2.4.1 PSEL Pin
            2. 8.2.3.2.4.2 CLKIO Pin
            3. 8.2.3.2.4.3 RT Pin
            4. 8.2.3.2.4.4 SS Pin
            5. 8.2.3.2.4.5 DIFFO Pin and FB Pin
            6. 8.2.3.2.4.6 COMP Pin
            7. 8.2.3.2.4.7 VSH Pin
            8. 8.2.3.2.4.8 Other Pins
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Stage
      2. 10.1.2 Device Peripheral
      3. 10.1.3 PowerPad Layout™
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGE Package
24-Pin VQFN
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 FB I Inverting input to the internal error amplifier. Normally this pin is at the reference voltage of 700 mV.
2 DIFFO O Output of the remote sense amplifier. Amplifier is fixed gain of 1 differential mode and is used for output voltage sensing at the load to eliminate distribution drops.
3 VOUT I Positive input to the remote sense amplifier. Amplifier is fixed gain of 1 differential mode and is used for output voltage sensing at the load to eliminate distribution drops.
4 GSNS I Negative input to the remote sense amplifier. Amplifier is fixed gain of 1 differential mode and is used for output voltage sensing at the load to eliminate distribution drops.
5 VSH I/O Pin is either an input or an output. If the chip is configured as a voltage loop master the valley voltage is output on this pin and is distributed to the slave devices. If configured as a voltage loop slave, the master VSH pin is connected here and the device uses the master valley voltage reference to improve current sharing.
6 ILIM I Programs the overcurrent limit of the device. Connecting a resistor from this pin to VSH and another to VOUT on the voltage loop master sets a voltage above VSH. COMP is not allowed to exceed this voltage. If the load current requirements force COMP to this level for seven clock cycles, an overcurrent event is declared, and the system shuts down and enter a hiccup fault recovery mode. The controller attempts to restart after a time period given by seven soft-start cycles.
7 SS I Soft-start input. This pin determines the startup ramp time for the converter as well as overcurrent and other fault recovery timing. The voltage at this pin is applied as a reference to the error amplifier. While this voltage is below the precision 700 mV reference, it acts as the dominant reference to the error amp providing a closed loop startup. After it rises above the 700 mV precision reference, the 700 mV precision reference dominates and the output regulates at the programmed level. In case of an overcurrent event, the converter attempts to restart after a period of time defined by seven soft-start cycles. Additionally this pin is used to configure the chip as a voltage loop master or slave. If the pin is tied to VDD or PVCC at power up, the device is in voltage loop slave mode. Otherwise, the device is a voltage loop master.
8 RT I Frequency programming pin. Connecting a resistor from this pin to GND sets the switching frequency of the device. If this pin is connected to VDD or PVCC, the device is a clock slave and gets its time base from CLKIO of the clock master device. Phase addressing is done on PSEL.
9 GND — Signal level ground connection for the device. All low level signals at the device should be referenced to this pin. No power level current should be allowed to flow through the GND pin copper areas on the board. Connect to the thermal pad area, and from there to the PGND copper area.
10 BP5 I Electrically quiet 5-V supply for the internal circuitry inside the device. If VDD is above 5 V, connect a 20-Ω resistor from PVCC to this pin and a 100-nF capacitor from this pin to GND. For VDD at 5 V, this pin can be tied directly to VDD or through a 20-Ω resistor with a 100-nF decoupling capacitor to reduce internal noise.
11 UVLO I UVLO input for the device. A resistor divider from VDD sets the turn on voltage for the device. Below this voltage, the device is in a low quiescent current state. Pulling this pin to ground shuts down the device, and is used as a system shutdown method.
12 VDD I Power input for the LDO on the device.
13 PGND — Common connection for the power circuits on the device. This pin should be electrically close to the source of the FET connected to LDRV. Connected to GND only at the thermal pad for best results.
14 LDRV O Gate drive output for the low-side or rectifier FET.
15 PVCC O Output of the on board LDO. This is the power input for the drivers and bootstrap circuit. The 5.3-V output on this pin is used for external circuitry as long as the total current required to drive the gates of the switching FETs and external loads is less than 50 mA. Connect a 1-µF capacitor from this pin to GND.
16 SW O This pin is connected to the source of the high-side or switch FET and is the return path for the floating high-side driver.
17 HDRV O Gate drive output for the high-side FET. High-side FET turn-on time must not be greater than minimum on-time. See electrical characteristics table for the minimum on time of the pulse width modulator.
18 BOOT I Bootstrap pin for the high-side driver. A 100-nF capacitor is connected from this pin to SW and provides power to the high-side driver when the high-side FET is turned on.
19 CLKIO I/O Clock and phase timing output while the device is configured as a clock master. In clock slave mode, the master CLKIO pin is connected to the slave CLKIO pin to provide time base information to the slave.
20 PGOOD O Power good output. This open drain output pulls low when the device is in any state other than in normal regulation. Active soft start, UVLO, overcurrent, undervoltage, overvoltage or overtemperature warning (115°C junction) causes this output to pull low.
21 PSEL I Phase select pin. For a clock master, a resistor from this pin to GND determines the CLKIO output. When configured as a clock slave, a resistor from the pin to GND selects the phase relationship that the slave has with the master. Allowing this pin to float causes the slave to drop off line to shed the phase when current demands are light for improved overall efficiency. See Detailed Description for more details.
22 CS+ I Positive input to the current sense amplifier.
23 CS– I Negative input to the current sense amplifier.
24 COMP O Output of the error amplifier.