JAJS234H MARCH   2007  – May 2019 TPS40192 , TPS40193

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Voltage Reference
      2. 8.3.2  Oscillator
      3. 8.3.3  UVLO
      4. 8.3.4  Enable Functionality
      5. 8.3.5  Start-Up Sequence and Timing
      6. 8.3.6  Selecting the Short Circuit Current
      7. 8.3.7  5-V Regulator
      8. 8.3.8  Prebias Start-Up
      9. 8.3.9  Drivers
      10. 8.3.10 Power Good
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conduction Mode
      2. 8.4.2 Low-Quiescent Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Selecting the Switching Frequency
        2. 9.2.2.2  Inductor Selection
        3. 9.2.2.3  Output Capacitor Selection (C8)
        4. 9.2.2.4  Peak Current Rating of the Inductor
        5. 9.2.2.5  Input Capacitor Selection (C7)
        6. 9.2.2.6  MOSFET Switch Selection (Q1, Q2)
        7. 9.2.2.7  Boot Strap Capacitor
        8. 9.2.2.8  Input Bypass Capacitor (C6)
        9. 9.2.2.9  BP5 Bypass Capacitor (C5)
        10. 9.2.2.10 Input Voltage Filter Resistor (R11)
        11. 9.2.2.11 Short Circuit Protection (R9)
        12. 9.2.2.12 Feedback Compensation (Modeling the Power Stage)
        13. 9.2.2.13 Feedback Divider (R7, R8)
        14. 9.2.2.14 Error Amplifier Compensation (R6, R10, C1, C2, C3)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 関連デバイス
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.3 Output Capacitor Selection (C8)

The selection of the output capacitor is typically driven by the output transient response. The Equation 8 and Equation 9 overestimate the voltage deviation to account for delays in the loop bandwidth and can be used to determine the required output capacitance.

Equation 8. TPS40192 TPS40193 q_vover_slus719.gif
Equation 9. TPS40192 TPS40193 q_vunder_slus719.gif

where

  • VIN(min) > 2 × VOUT, use overshoot to calculate minimum output capacitance.
  • VIN(min) < 2 × VOUT, use undershoot to calculate minimum output capacitance.
Equation 10. TPS40192 TPS40193 q_coutmin_slus719.gif

With a minimum capacitance, the maximum allowable ESR is determined by the maximum ripple voltage and is approximated by Equation 11.

Equation 11. TPS40192 TPS40193 q_esrmax1_slus719.gif

Two 1206 100-μF, 6.3-V X5R ceramic capacitors are selected to provide more than 178-μF of minimum capacitance and less than 4.4 mΩ of ESR (2.5 mΩ each).