JAJS234H MARCH   2007  – May 2019 TPS40192 , TPS40193

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Voltage Reference
      2. 8.3.2  Oscillator
      3. 8.3.3  UVLO
      4. 8.3.4  Enable Functionality
      5. 8.3.5  Start-Up Sequence and Timing
      6. 8.3.6  Selecting the Short Circuit Current
      7. 8.3.7  5-V Regulator
      8. 8.3.8  Prebias Start-Up
      9. 8.3.9  Drivers
      10. 8.3.10 Power Good
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conduction Mode
      2. 8.4.2 Low-Quiescent Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Selecting the Switching Frequency
        2. 9.2.2.2  Inductor Selection
        3. 9.2.2.3  Output Capacitor Selection (C8)
        4. 9.2.2.4  Peak Current Rating of the Inductor
        5. 9.2.2.5  Input Capacitor Selection (C7)
        6. 9.2.2.6  MOSFET Switch Selection (Q1, Q2)
        7. 9.2.2.7  Boot Strap Capacitor
        8. 9.2.2.8  Input Bypass Capacitor (C6)
        9. 9.2.2.9  BP5 Bypass Capacitor (C5)
        10. 9.2.2.10 Input Voltage Filter Resistor (R11)
        11. 9.2.2.11 Short Circuit Protection (R9)
        12. 9.2.2.12 Feedback Compensation (Modeling the Power Stage)
        13. 9.2.2.13 Feedback Divider (R7, R8)
        14. 9.2.2.14 Error Amplifier Compensation (R6, R10, C1, C2, C3)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 関連デバイス
      2. 12.1.2 デバイスの項目表記
    2. 12.2 ドキュメントのサポート
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.6 MOSFET Switch Selection (Q1, Q2)

The switching losses for the high-side MOSFET are estimated by Equation 17.

Equation 17. TPS40192 TPS40193 q_pg1sw_slus719.gif

Switching losses in this design are highest at high-line. Designing for 1 W of total loss in each MOSFET and 60% of the total high-side MOSFET losses in switching losses, estimate the maximum gate-drain charge for the design by using Equation 18.

Equation 18. TPS40192 TPS40193 q_gd1max_slus719.gif

The switching losses of the synchronous rectifier are lower than the switching losses of the main MOSFET because the voltage across the MOSFET at the point of switching is reduced to the forward voltage drop across the body diode of the SR MOSFET and are estimated by using Equation 19. The conduction losses in the main MOSFET are estimated by the RMS current through the MOSFET times its RDS(on).

Equation 19. TPS40192 TPS40193 q_pg1con_slus719.gif

Estimating about 40% of total MOSFET losses to be high-side conduction losses, the maximum RDS(on) of the high-side MOSFET can be estimated by using Equation 20.

Equation 20. TPS40192 TPS40193 q_rdsonq1max_slus719.gif

Estimating 80% of total low-side MOSFET losses in conduction losses, repeat the calculation for the synchronous rectifier, whose losses are dominated by the conduction losses. Calculate the maximum RDS(on) of the synchronous rectifier by Equation 21.

Equation 21. TPS40192 TPS40193 q_rdsonq2max_slus719.gif

Table 4. Power MOSFET Requirements

PARAMETER SYMBOL VALUE UNITS
High-side MOSFET on-resistance RDS(on)Q1 30.9 mΩ
High-side MOSFET gate-to-drain charge QGD1 8.5 nC
Low-side MOSFET on-resistance RDS(on)Q2 8.8 mΩ

The IRF7466 has an RDS(on)MAX of 30.9 mΩ at 4.5-V gate drive and only 8.0-nC VGD "Miller" charge with a 4.5-V gate drive, and is chosen as a high-side MOSFET. The IRF7834 has an RDS(on)Q1,MAX of 5.5 mΩ at 4.5-V gate drive and 44 nC of total gate charge. These two FETs have maximum total gate charges of 23 nC and 44 nC respectively, which draws 40.2-mA from the 5-V regulator, less than its 50-mA minimum rating.