SLUS772G March   2008  – June 2020 TPS40210 , TPS40211

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Soft Start
      2. 7.3.2  BP Regulator
      3. 7.3.3  Shutdown (DIS/ EN Pin)
      4. 7.3.4  Minimum On-Time and Off-Time Considerations
      5. 7.3.5  Setting the Oscillator Frequency
      6. 7.3.6  Synchronizing the Oscillator
      7. 7.3.7  Current Sense and Overcurrent
      8. 7.3.8  Current Sense and Subharmonic Instability
      9. 7.3.9  Current Sense Filtering
      10. 7.3.10 Control Loop Considerations
      11. 7.3.11 Gate Drive Circuit
      12. 7.3.12 TPS40211
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum Input Voltage
      2. 7.4.2 Operation With DIS/ EN Pin
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 12-V to 24-V Nonsynchronous Boost Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design with WEBENCH Tools
          2. 8.2.1.2.2  Duty Cycle Estimation
          3. 8.2.1.2.3  Inductor Selection
          4. 8.2.1.2.4  Rectifier Diode Selection
          5. 8.2.1.2.5  Output Capacitor Selection
          6. 8.2.1.2.6  Input Capacitor Selection
          7. 8.2.1.2.7  Current Sense and Current Limit
          8. 8.2.1.2.8  Current Sense Filter
          9. 8.2.1.2.9  Switching MOSFET Selection
          10. 8.2.1.2.10 Feedback Divider Resistors
          11. 8.2.1.2.11 Error Amplifier Compensation
          12. 8.2.1.2.12 RC Oscillator
          13. 8.2.1.2.13 Soft-Start Capacitor
          14. 8.2.1.2.14 Regulator Bypass
          15. 8.2.1.2.15 Bill of Materials
        3. 8.2.1.3 Application Curves
      2. 8.2.2 12-V Input, 700-mA LED Driver, Up to 35-V LED String
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2.      65
      3. 11.1.2 Related Devices
      4. 11.1.3 Development Support
        1. 11.1.3.1 Custom Design with WEBENCH Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1.     78

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • DRC|10
  • DGQ|10
サーマルパッド・メカニカル・データ

Revision History

Changes from Revision F (March 2015) to Revision G (June 2020)

Changes from Revision E (October 2011) to Revision F (December 2014)

  • Added Updated Land PatternGo
  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from Revision D (April 2010) to Revision E (October 2011)

  • Changed the Revision date from D, April 2010 to E, October 2011Go
  • Added Q1 and Q3 to Figure 36 by illustratorGo

Changes from Revision C (October 2008) to Revision D (April 2010)

  • Changed CISNS to CIFLT Go
  • Changed CISNS to CIFLT Go
  • Changed equations 22 and 23Go
  • Changed corrected equation 25Go
  • Added "R1 is the high side feedback resistor in Ω" and " fL is the desired loop crossover frequency, in Hz"Go
  • Changed paragraph with new inputGo
  • Changed capacitor value from µF to FGo
  • Changed 0.2 with 0.1 in MIN col in Design Example Specifications tableGo
  • Deleted text from Peak efficiency rowGo
  • Changed 10 V with 8 V in TOP conditions columnGo
  • Deleted 0.2 V ≤ in TOP conditions columnGo
  • Changed 42.8% to 42.9% in eq 32Go
  • Added (VFD) and changed approximate duty cycle from 42.8% to 42.9%Go
  • Changed equations 32, 34, 35, 36, 37, 38 and 39Go
  • Changed equations 47, 48, 49, 50, 51 and 53Go
  • Changed equations 58, 60, 61, 62Go