JAJSR60F August   2008  – June 2020 TPS40210-Q1 , TPS40211-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5.   5
  6. Revision History
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  9. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum On-Time and Off-Time Considerations
      2. 7.3.2  Current Sense and Overcurrent
      3. 7.3.3  Current Sense and Subharmonic Instability
      4. 7.3.4  Current Sense Filtering
      5. 7.3.5  Soft Start
      6. 7.3.6  BP Regulator
      7. 7.3.7  Shutdown (DIS/ EN Pin)
      8. 7.3.8  Control Loop Considerations
      9. 7.3.9  Gate Drive Circuit
      10. 7.3.10 TPS40211-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Setting the Oscillator Frequency
      2. 7.4.2 Synchronizing the Oscillator
  10. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Duty Cycle Estimation
        2. 8.2.2.2  Inductor Selection
        3. 8.2.2.3  Rectifier Diode Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Current Sense and Current Limit
        7. 8.2.2.7  Current Sense Filter
        8. 8.2.2.8  Switching MOSFET Selection
        9. 8.2.2.9  Feedback Divider Resistors
        10. 8.2.2.10 Error Amplifier Compensation
        11. 8.2.2.11 R-C Oscillator
        12. 8.2.2.12 Soft-Start Capacitor
        13. 8.2.2.13 Regulator Bypass
      3. 8.2.3 Application Curves
  11. Power Supply Recommendations
  12. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  13. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 サポート・リソース
    6. 11.6 Trademarks
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 用語集
  14. 12Mechanical, Packaging, and Orderable Information
    1.     70

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • DGQ|10
サーマルパッド・メカニカル・データ
発注情報

Control Loop Considerations

There are two methods to design a suitable control loop for the TPS4021x device. The first (and preferred, if equipment is available) is to use a frequency-response analyzer to measure the open-loop modulator and power stage gain and to then design compensation to fit that. The usage of these tools for this purpose is well-documented with the literature that accompanies the tool and is not discussed here.

The second option is to make an initial guess at compensation, and then evaluate the transient response of the system to see if the compensation is acceptable to the application or not. For most systems, an adequate response can be obtained by simply placing a series resistor and capacitor (RFB and CFB) from the COMP pin to the FB pin as shown in Figure 7-6.

GUID-D3213B8E-D6A4-450F-8029-A586557F6FEC-low.gifFigure 7-6 Basic Compensation Network

The natural phase characteristics of most capacitors used for boost outputs combined with the current mode control provide adequate phase margin when using this type of compensation. To determine an initial starting point for the compensation, the desired crossover frequency must be considered when estimating the control to output gain. The model used is a current source into the output capacitor and load.

When using these equations, the loop bandwidth should be no more than 20% of the switching frequency, fSW. A more reasonable loop bandwidth would be 10% of the switching frequency. Be sure to evaluate the transient response of the converter over the expected load range to ensure acceptable operation.

Equation 21. GUID-7D5F9D1A-ABDD-4A2A-97D9-200CC9FD2EE9-low.gif
Equation 22. GUID-90FC57DB-2AA3-47D7-BE41-D51544D5598D-low.gif
Equation 23. GUID-42D102AE-CBEA-4E9B-BE63-7FD458C321B4-low.gif

where

  • KCO is the control to output gain of the converter, in V/V
  • gM is the transconductance of the power stage and modulator, in S
  • ROUT is the output load equivalent resistance, in Ω
  • ZOUT is the output impedance, including the output capacitor, in Ω
  • RISNS is the value of the current sense resistor, in Ω
  • L is the value of the inductor, in H
  • COUT is the value of the output capacitance, in μF
  • RESR is the equivalent series resistance of COUT, in Ω
  • fSW is the switching frequency, in Hz
  • fL is the desired crossover frequency for the control loop, in Hz

These equations assume that the operation is discontinuous and that the load is purely resistive. The gain in continuous conduction can be found by evaluating Equation 22 at the resistance that gives the critical conduction current for the converter. Loads that are more like current sources give slightly higher gains than predicted here. To find the gain of the compensation network required for a control loop of bandwidth fL, take the reciprocal of Equation 21.

Equation 24. GUID-0514E67A-1BE8-4E44-8EFA-77366B33E014-low.gif

The GBWP of the error amplifier is only specified to be at least 1.5 MHz. If KCOMP multiplied by the fL is greater than 750 kHz, reduce the desired loop crossover frequency until this condition is satisfied. This ensures that the high-frequency pole from the error amplifier response with the compensation network in place does not cause excessive phase lag at the fL and decrease phase margin in the loop.

The R-C network connected from COMP to FB places a zero in the compensation response. That zero should be approximately 1/10th of the desired crossover frequency, fL. With that being the case, RFB and CFB can be found from Equation 25 and Equation 26.

Equation 25. GUID-3CA3F67A-18EC-468E-8312-7C7E9AFA11D6-low.gif
Equation 26. GUID-2C14745D-DEFF-4F8E-BFE2-9870BDC2A2FD-low.gif

where

  • R1 is in fL is the loop crossover frequency desired, in Hz
  • RFB is the feedback resistor in CFB is the feedback capacitance in μF

Though not strictly necessary, it is recommended that a capacitor be added between COMP and FB to provide high-frequency noise attenuation in the control loop circuit. This capacitor introduces another pole in the compensation response. The allowable location of that pole frequency determines the capacitor value. As a starting point, the pole frequency should be 10 × fL. The value of CHF can be found from Equation 27.

Equation 27. GUID-0E600C04-7AB7-4113-A208-105DF07BAC64-low.gif

The error amplifier GBWP will usually be higher, but is ensured by design to be at least 1.5 MHz. If the gain required in Equation 24 multiplied by 10 times the desired control loop crossover frequency, the high-frequency pole introduced by CHF is overridden by the error amplifier capability and the effective pole is lower in frequency. If this is the case, CHF can be made larger to provide a consistent high-frequency roll off in the control loop design. Equation 28 calculates the required CHF in this case.

Equation 28. GUID-78E86BFB-3025-432B-A31B-E6D91CBE2617-low.gif

where

  • CHF is the high-frequency roll-off capacitor value in μF
  • RFB is the mid-band gain-setting resistor value in Ω