JAJSR60F August 2008 – June 2020 TPS40210-Q1 , TPS40211-Q1
PRODUCTION DATA
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There are two methods to design a suitable control loop for the TPS4021x device. The first (and preferred, if equipment is available) is to use a frequency-response analyzer to measure the open-loop modulator and power stage gain and to then design compensation to fit that. The usage of these tools for this purpose is well-documented with the literature that accompanies the tool and is not discussed here.
The second option is to make an initial guess at compensation, and then evaluate the transient response of the system to see if the compensation is acceptable to the application or not. For most systems, an adequate response can be obtained by simply placing a series resistor and capacitor (RFB and CFB) from the COMP pin to the FB pin as shown in Figure 7-6.
The natural phase characteristics of most capacitors used for boost outputs combined with the current mode control provide adequate phase margin when using this type of compensation. To determine an initial starting point for the compensation, the desired crossover frequency must be considered when estimating the control to output gain. The model used is a current source into the output capacitor and load.
When using these equations, the loop bandwidth should be no more than 20% of the switching frequency, fSW. A more reasonable loop bandwidth would be 10% of the switching frequency. Be sure to evaluate the transient response of the converter over the expected load range to ensure acceptable operation.
where
These equations assume that the operation is discontinuous and that the load is purely resistive. The gain in continuous conduction can be found by evaluating Equation 22 at the resistance that gives the critical conduction current for the converter. Loads that are more like current sources give slightly higher gains than predicted here. To find the gain of the compensation network required for a control loop of bandwidth fL, take the reciprocal of Equation 21.
The GBWP of the error amplifier is only specified to be at least 1.5 MHz. If KCOMP multiplied by the fL is greater than 750 kHz, reduce the desired loop crossover frequency until this condition is satisfied. This ensures that the high-frequency pole from the error amplifier response with the compensation network in place does not cause excessive phase lag at the fL and decrease phase margin in the loop.
The R-C network connected from COMP to FB places a zero in the compensation response. That zero should be approximately 1/10th of the desired crossover frequency, fL. With that being the case, RFB and CFB can be found from Equation 25 and Equation 26.
where
Though not strictly necessary, it is recommended that a capacitor be added between COMP and FB to provide high-frequency noise attenuation in the control loop circuit. This capacitor introduces another pole in the compensation response. The allowable location of that pole frequency determines the capacitor value. As a starting point, the pole frequency should be 10 × fL. The value of CHF can be found from Equation 27.
The error amplifier GBWP will usually be higher, but is ensured by design to be at least 1.5 MHz. If the gain required in Equation 24 multiplied by 10 times the desired control loop crossover frequency, the high-frequency pole introduced by CHF is overridden by the error amplifier capability and the effective pole is lower in frequency. If this is the case, CHF can be made larger to provide a consistent high-frequency roll off in the control loop design. Equation 28 calculates the required CHF in this case.
where