7.3.1 Unregulated Battery Input Voltage (VBAT)

This input terminal will have an external input filter and voltage suppression above 40 V for protection. The input is used to provide the operating voltage for the high side driver output, and used for sensing over voltage condition in the system. The over voltage detection circuitry has hysteresis for noise rejection.

7.3.2 Protected Unregulated Battery Input Voltage (VBATP)

This terminal provides the power source for internal circuitry to bias band-gap reference, oscillator and other circuitry in the device. The voltage on this terminal is used to sense for system undervoltage condition.

7.3.3 Low-Voltage Warning Input (LVWIN)

This input is used to detect low voltage condition. The input voltage source is scaled using external resistor network (programmable) to set the threshold for detection of low voltage condition. Once the input voltage is below the set threshold the low voltage warning output terminal is pulled low (VBATW).

7.3.4 Voltage Warning Output (VBATW)

This is an open drain output which is pulled up to supply with an external resistor. This output is asserted low when either of the following conditions is satisfied:

• Detection of low-voltage condition
• Detection of overvoltage condition

If the fault condition is removed the VBATW output is deasserted (output goes high).

7.3.5 Low-Voltage Reset (RST)

This output indicates if there is a low voltage on the standby regulator output (VSTBY). The output is deasserted once the standby regulator achieves proper regulation and after the power delay timer has expired. This low voltage reset circuitry is functional for voltages above 0.5 V on the standby regulator output terminal. Additionally the low voltage reset output will remain low if the standby regulator input voltage is in the undervoltage lockout mode. If the PGDLY and VSTBYS pins are both high, the nRST pin is high. The VSTBYS voltage must be higher than 0.93 V (typical) and the nRST pin is pulled low 10 µs (typical) after the VSTBYS pin goes low.

7.3.6 Power-Good Delay Timer Input (PGDLY)

The capacitor on this terminal programs power good delay timer function. A current source on this pin charges an external capacitor once the standby regulator achieves proper regulation. Once the voltage on the capacitor exceeds the internal threshold the internal comparator will deassert the reset output line. The external capacitor is discharged (reset) once the RST output is deasserted, and so any subsequent power up sequence will start from zero time for the power good delay. The power good delay is not initiated as a result of external device asserting the reset output terminal.

7.3.7 Active Mode Enable Input (EN)

This input pin commands different modes of operation. When asserted low the device will enter low quiescent standby mode, with only the standby regulator ON. Once the input is asserted high the device is in active mode and regulator output control is achieved by discrete inputs and serial communications. The input is TTL-compatible with hysteresis for noise rejection. There is an internal pull down to ensure a default state of standby mode.

7.3.8 Slew Rate Control Capacitor Input (CSLEW)

This pin provides the soft-start function for an internal reference used by the standby linear voltage regulator. An internal current source will charge an external capacitor to produce a linear voltage ramp at start up for the internal reference. This will be used to limit the slew rate of the output voltage of the standby regulator. An internal low side switch is used to discharge the capacitor in accordance will the operating mode requirements for slew rate control.

The soft start time must be greater than dtss > 2π (LC)^1/2.

7.3.9 Charge Pump Capacitor Input (VCP)

This pin has an external capacitor to provide storage for an internal charge pump.

This charge pump is activated at supply voltages less than approximately 9 V to appropriately supply the high-side driver. When active, the quiescent current is increased.

7.3.10 Power Ground (PGND)

This pin is the power ground reference for the device. All switching nodes are referenced to this ground.

7.3.11 Analog Ground Reference (AGND)

This pin is reference ground for ALL non-power and non-switch-mode related ground termination inside the device.

7.3.12 Inter-IC Communications Interface (I2CID)

The serial communications interface is a 7-bit address for controlling the switch mode controller 2 (VBUCK 2), linear regulator (VLR) and high side driver output (HSD). There are two lines SCL and SDA to control the communications between the master and the slave. An I2CID terminal is used to address the IC in a system where multiple IC’s may be implemented. The SDA terminal has an internal FET switch to pull the SDA low as an acknowledgment signal back to the main controller. An active high allows access to the register.

7.3.13 Clock Input (SCL)

This pin is an input pin for a clock signal input from the master control. The clock signal is used to synchronize the data communications between the master device and the slave (TPS43331-Q1). The input signal will be TTL-compatible with hysteresis for noise rejection.

7.3.14 Data Line (SDA)

The pin is a data line communications between the master and slave device. The input signal is TTL-compatible with hysteresis for noise rejection. An internal pull down driver will provide an acknowledgment signal back to the master controller.

7.3.15 Interface Chip Identifier (I2CID)

The pin is used as a chip identification input for the I²C interface between the master and the slave device. The input signal is TTL-compatible with hysteresis for noise rejection. The state of the input signal is reflected in the I²C chip address byte 0. The value of the signal on this terminal is latched on a POR condition. A low leakage internal pull-down is implemented to ensure the default state is zero.

The device requires a three-byte access from the microcontroller (Chip address, Register address and data).

7.3.16 Switch Mode Regulators

There are two switch-mode controllers when configured with external power switches form the buck (step-down) regulators. One switch-mode regulator is controlled by an enable input control (EN) and the second is controlled by a bit using the serial communications interface.

Short-circuit detection is achieved by current sensed through an external sense resistor in series with the inductor. The current limit is applied on a cycle-by cycle basis. Once overcurrent is detected the output is disabled for the remainder of the cycle, and is enabled on the next clock edge.

7.3.17 Upper FET Gate Drive Outputs (VGT1 and VGT2)

These outputs are the gate drive signals for the external high side FETs for each switch-mode controller.

The output voltage is clamped to prevent excessive gate drive voltage to the external MOS devices. These outputs are a push-pull configuration and are current limited for charging a capacitive load.

7.3.18 Lower FET Gate Driver Outputs (VGB1 and VGB2)

These outputs are the gate drive signals for the external low side FETs for each switch-mode controller. The switching signal is 180 degrees out of phase with the upper gate drive signals for each controller. The lower gate drive controls the FET for synchronous switching. These output signals are clamped to prevent excessive gate voltage to the external MOS devices. These outputs are a push-pull configuration and are current limited for charging a capacitive load.

7.3.19 Bootstrap Capacitor Input (CBS1 and CBS2)

These pins are the bootstrap capacitor inputs for switcher 1 and switcher 2 respectively. These capacitors act as the voltage supply for the upper gate drive circuitry. The capacitors are re-charged on every low side synchronous switching action. In the case of 100% duty cycle for the upper FET, the device will automatically reduce the duty cycle to approximately 95% on every fifth cycle to allow these capacitors to re-charge.

7.3.20 Phase Reference for High-Side Bootstrap Supply (PH1 and PH2)

These pins provide a floating voltage reference for the high-side FET gate drive circuitry for switcher 1 and switcher 2 respectively. These nodes are used to monitor the status of the upper external FETs, and allow switching of the lower external FETs without shorting the supply.

7.3.21 Current Sense High-Side (ISHI1 and ISHI2)

These are the high-side current sense resistor node inputs for switcher 1 and switcher 2 respectively. The common mode range of the combined high-side and low-side current sense inputs supports the entire output voltage range.

7.3.22 Current Sense Low-Side (ISLO1 and ISLO2)

These are the low-side current sense resistor node inputs for switcher 1 and switcher 2 respectively. The common mode range of the combined high-side and low-side current sense inputs supports the entire output voltage range.

7.3.23 Regulated Output Sense Voltage Feedback (VFB1 and VFB2)

These are the input pins for the voltage output feedback signals for switcher 1and switcher 2 respectively. The external resistor network setting on these pins programs the desired regulated output voltages for each switch-mode converter.

7.3.24 Feedback Compensation Input (VCMP1 and VCMP2)

These are the input pins for the converter compensation feedback for switcher 1 and switcher 2 respectively.

7.3.25 Synchronization Input (SYNCH)

This is an input pin for feeding an external clock to synchronize the switching frequency of both switch-mode regulators. The IC will detect a small number of edges (2 to 5) prior to recognizing a valid external clock input signal and synchronizing the internal operation with an external clock input. The regulator operates with an external input clock signal until a low voltage reset or a command to go into a sleep mode.

7.3.26 Standby Linear Regulator Input (VINSB)

This is the input pin for the operating voltage of the standby regulator. The voltage source for the standby regulator requires an external blocking diode in the module for reverse supply conditions. This input pin requires the necessary filtering and protection against positive and negative transients to prevent damage to the IC (see Figure 16).

7.3.27 Standby Regulator Output (VSTBY)

This is the regulated output of the standby regulator, and derives the voltage source from the VINSB terminal. The regulator has an internal linear current limit for protection against shorts to ground. The output voltage will recover to the specified range once the fault condition is removed. This output remains within the tolerance of the specification during positive transient events on the input. An under-shoot condition during any load transient event will not assert a reset condition on the RST output, proving the load transient is within the specified range.

Once the regulator drops-out due to low input voltage on VINSB, the output tracks the input voltage minus the saturation voltage of the pass device. The device will enter thermal shut down if the local die temperature exceeds the thermal shut-down threshold. The thermal shut-down has hysteresis such that the output enables once the local die temperature falls below the disable threshold. If the output falls below the specified low voltage reset, the IC will notify this condition by asserting the rest line RST low.

7.3.28 Standby Regulator Sense Voltage (VSTBYS)

This pin is used to program the regulated output voltage to a range specified in the parametric table. An external resistor network is used to ratio the output voltage and fed back into the VSTBYS pin.

7.3.29 Switched Linear Regulator Input (VINLR)

This is the input pin for the operating voltage of the switched linear regulator. The voltage source for this regulator requires an external blocking diode in the module for reverse supply conditions. This input pin requires the necessary filtering and protection against positive and negative transients to prevent damage to the IC (see Figure 16).

7.3.30 Switched Linear Regulator Output (VLR)

This is the regulated output of the switched linear regulator, and derives the voltage source from the VINLR terminal. The regulator has an internal linear current limit for protection against shorts to ground. The output voltage will recover to the specified range, once the fault condition is removed. This output remains within the tolerance of the specification during load transient event on the output line. The output is disabled in the event VBAT exceeding the overvoltage shut-down threshold VOVSD. The output will be enabled once the VBAT input voltage falls below the internal set threshold (with hysteresis).

Once the regulator drops-out due to low input voltage on VINLR, the output tracks the input voltage minus the saturation voltage of the pass device. The device will enter thermal shut down if the local die temperature exceeds the thermal shut-down threshold. The thermal shut-down has hysteresis such that the output enables once the local die temperature falls below the disable threshold.

7.3.31 Switched Linear Regulator Sense Voltage (VLRS)

This pin is used to program the regulated output voltage to a range specified in the parametric table. An external resistor network is used to ratio the output voltage and fed back into the VLRS pin.

7.3.32 High-Side Driver Output (HSD)

This pin is the output of the high side driver (switched input voltage). The output is enabled through a bit in the I2C data register. If the voltage on the VBAT supply exceed the overvoltage shutdown threshold VOVSD this output is disabled. Upon return from the fault condition the output recovers to the state set by the enable bit (HSDEN) in I²C data register without any intervention from the system. The output is stable during any soft-start conditions or specified load transients. This output is protected against:

• Short to module supply
• Short to module ground
• Short through the load to –1 V
• Unpowered short to module supply
• Reverse supply (–13 V)

The output has short circuit protection with a linear current limit and thermal shutdown with hysteresis.

If the local die temperature exceeds the thermal shutdown detection threshold this output is disabled. This output is enabled once the local die temperature falls below the detection threshold with hysteresis providing the HSDEN bit is set.

The invoking of thermal shut down on this output does not directly affect any other outputs or circuitry in the IC. The operation of the switch is not affected during the re-circulation of an inductive load providing the negative voltage applied to this pin is within the specified limits

7.4.1 Operating Mode Definition

Figure 17 shows the operating modes of the TPS43331-Q1.

Figure 17. Operating Modes

7.5.1 Register Definition for I²C

7.5.1.1 Chip Address Byte

The IC supports two addresses by using bit 4 of the chip address byte and the I2CID input. The state of the I2CID input pin is read into bit 3 of the chip address byte (indicated by X in the frame above).

The valid chip addresses for writing to this IC are $0001000 (0x08) and $0001100 (0x0C), since the LSB of the chip address byte is a read/write bit, these two addresses translate into hex values of 0x10 and 0x18 respectively.

Frame format requires two-byte access from the master controller.

• The first byte contains the address information
• The second byte contains the data information

Table 1. Frame Format

	CHIP ADDRESS BYTE 0									REGISTER ADDRESS									DATA BYTE 0
S	0	0	0	1	X	0	0	0	A	0	0	0	0	0	0	0	1	A	7	6	5	4	3	2	1	0	A	P
	MSB							LSB

The data format/transfer will be the following order:

1. MSB first to LSB last; Bit 7 of each byte is the MSB. Bit 0 of each byte is the LSB.
2. Bit 0 (LSB) in the address byte defines the read/write bit; a value of 0 indicates a data write.
3. The bit marked X in the address byte indicates the state of the I2CID input.

Transmission format:

1. The data transfer begins with a start signal (S), where the SDA transitions from high to low while SCL is high (see Figure 18).
2. After 8 bits are transmitted and detected the IC (TPS43331-Q1) will send an acknowledge pulse (A) to the master.
3. After each successive writes of 8 bits, the IC sends an acknowledge pulse to the master.
4. The message communications is completed (stop condition P) when SDA transitions from low to high while SCL is high.

1. Bit 8 is used for read or writer options, with:
Bit 8 = 1 is read
Bit 8 = 0 is write

Figure 18. I²C Communications

If a transfer is interrupted by a stop condition, the partial byte transmission shall not be latched. Only the prior messages transmitted and acknowledged are latched.

7.6.1 Data Register