JAJSOQ0 December   2023 TPS4800-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, PU, PD, BST, SRC)
      2. 7.3.2 Capacitive Load Driving Using FET Gate (PU, PD) Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Overvoltage (OV) and Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 7.3.7 TPS48000-Q1 as a Simple Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Limitations
        1. 8.1.1.1 Short-Circuit Protection Delay
        2. 8.1.1.2 Short-Circuit Protection Threshold
    2. 8.2 Typical Application: Driving Power at all Times (PAAT) Loads
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3.1 Short-Circuit Protection With Auto-Retry

The CTMR programs the short-circuit protection delay (tSC) and auto-retry time (tRETRY). Once the voltage across CS+ and CS– exceeds the set point, the CTMR starts charging with 80-μA pull-up current.

After CTMR charges to V(TMR_SC), PD pulls low to SRC and FLT asserts low providing warning on impending FET turn OFF. Post this event, the auto-retry behavior starts. The CTMR capacitor starts discharging with 2.5-uA pulldown current. After the voltage reaches V(TMR_LOW) level, the capacitor starts charging with 2.2-uA pullup. After 32 charging-discharging cycles of CTMR the FET turns ON back and FLT de-asserts.

The device retry time (tRETRY) is based on CTMR for the first time as per Equation 7.

Use Equation 6 to calculate the CTMR capacitor to be connected across TMR and GND.

Equation 6. C T M R = I T M R   ×   t S C 1.1

Where,

ITMR is internal pull-up current of 80-μA.

tSC is desired short-circuit response time.

Leave TMR floating for fastest short-circuit response time.

Equation 7. tRETRY= 22.7 × 106 × CTMR

If the short-circuit pulse duration is below tSC then the FET remains ON and CTMR gets discharged using internal pull down switch.

GUID-20230517-SS0I-ZTTK-P7ST-MWG78PDRHDDZ-low.svgFigure 7-9 Short-Circuit Protection With Auto-Retry