JAJSOG7 January   2024 TPS4810-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, G2, BST, SRC)
      2. 7.3.2 Capacitive Load Driving Using FET Gate (G1PU, G1PD) Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 7.3.7 TPS48100-Q1 as a Simple Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Limitations
        1. 8.1.1.1 Short-Circuit Protection Delay
        2. 8.1.1.2 Short-Circuit Protection Threshold
    2. 8.2 Typical Application: Circuit Breaker in Battery Management System (BMS) using Low Side Current Sense
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Switching Characteristics

TJ = –40 ℃ to +125℃. V(VS) = 48 V, V(BST – SRC) = 11 V, V(SRC) = 0 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tG1PU(INP1_H) INP1 turn on propogation Delay INP1 ↑ to G1PU  ↑,  CL = 47 nF 1 µs
tG2(INP2_H) INP2 turn on propogation Delay INP2 ↑ to G2  ↑,  CL = 47 nF 5 µs
tG1PD(INP1_L) INP1 turn off propogation Delay INP1 ↓ to G1PD  ↓, CL = 47 nF 1 µs
tG2(INP2_L) INP2 turn off propogation Delay INP2 ↓ to G2  ↓, CL = 47 nF 5 µs
tPD(UVLO_OFF) UVLO turn off propogation Delay  UVLO ↓ to G1PD  ↓, CL = 47 nF 7.5 µs
tPD(IFLT_OFF) Hard short-circuit protection propogation Delay  V(CS+–CS–)↑ V(SCP) to G1PD  ↓, CL = 47 nF, C(TMR) = Open 4 µs
tSC_PUS Short circuit protection propogation delay during power up with output short circuit C(TMR) = Open 10 µs