SLUSFM1 December 2024 TPS4812-Q1
PRODUCTION DATA
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When the external MOSFETs turn-OFF during the conditions such as INP control, overcurrent or short-circuit protection causing an interruption of the current flow, the input parasitic line inductance generates a positive voltage spike on the input and output parasitic inductance generates a negative voltage spike on the output. The peak amplitude of voltage spikes (transients) depends on the value of inductance in series to the input or output of the device. These transients can exceed the Absolute Maximum Ratings of the device if steps are not taken to address the issue. Typical methods for addressing transients include:
Use of a TVS diode and input capacitor filter combination across input to and GND to absorb the energy and dampen the positive transients.
Use of a diode or a TVS diode across the output and GND to absorb negative spikes.
The TPS4812-Q1 gets powered from the VS pin. Voltage at this pin must be maintained above V(VS_PORR) level to ensure proper operation. If the input power supply source is noisy with transients, then TI recommends to place a RVS – CVS filter between the input supply line and VS pin to filter out the supply noise. TI recommends an RVS value around 100-Ω and CVS value around 0.1 µF.
TPS4812-Q1 uses DRN pin for sensing input reverse polarity fault event. If the input power supply source is noisy with transients, then TI recommends to place a RDRN – CDRN filter between the input supply line and DRN pin to filter out the supply noise. TI recommends an RDRN value around 10-Ω and CDRN value around 0.1 µF.
In a case where large di/dt is involved, the system and layout parasitic inductances can generate large differential signal voltages between CS1+ and CS1– pins. This action can trigger false short-circuit protection and nuisance trips in the system. To overcome such scenario, TI suggests to add a placeholder for RC filter components across the sense resistor (RSNS) and tweak the values during test in the real system.
Figure 9-19 shows the circuit implementation with optional protection components.