SLUSFM1 December 2024 TPS4812-Q1
PRODUCTION DATA
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The CI2t programs the over current protection delay (tOC_MIN) and CTMR programs auto-retry time (tRETRY). Once the voltage across CS1+ and CS1– exceeds the set point (V(OCP)), the CI2t capacitor starts charging with current proportional to ILOAD2 – IOC2 current.
After CI2t charges to V(I2t_OC), GATE pulls low to SRC turning OFF the main FET and FLT assets low as same time. Post this event, the auto-retry behavior starts. The CTMR starts charging with 2.5µA pullup current till voltage reaches V(TMR_HIGH) level. After this level, capacitor starts discharging with 2.5µA pulldown current.
After the voltage reaches V(TMR_LOW) level, the capacitor starts charging again with 2.5µA pullup. After 32 charging-discharging cycles of CTMR the FET turns ON back and FLT de-asserts after de-assertion delay.
The auto-retry time can be set by CTMR capacitor to be connected across TMR and GND pins as per Equation 13.
where
V(TMR_HIGH) is 1.2V (typ) and V(TMR_LOW) is 0.2V (typ).
I(TMR_SRC) is internal source current on TMR pin with 2.5µA (typ) value.