SLUSFM1 December   2024 TPS4812-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Charge Pump and Gate Driver Output (VS, GATE, BST, SRC)
      2. 8.3.2 Capacitive Load Driving
        1. 8.3.2.1 Using Low-Power Bypass FET (G Drive) for Load Capacitor Charging
        2. 8.3.2.2 Using Main FET (GATE Drive) Gate Slew Rate Control
      3. 8.3.3 Overcurrent and Short-Circuit Protection
        1. 8.3.3.1 I2t-Based Overcurrent Protection
          1. 8.3.3.1.1 I2t-Based Overcurrent Protection With Auto-Retry
          2. 8.3.3.1.2 I2t-Based Overcurrent Protection With Latch-Off
        2. 8.3.3.2 Short-Circuit Protection
      4. 8.3.4 Analog Current Monitor Output (IMON)
      5. 8.3.5 NTC-Based Temperature Sensing (TMP) and Analog Monitor Output (ITMPO)
      6. 8.3.6 Fault Indication and Diagnosis (FLT)
      7. 8.3.7 Reverse Polarity Protection
      8. 8.3.8 Undervoltage Protection (UVLO)
    4. 8.4 Device Functional Modes
      1. 8.4.1 State Diagram
      2. 8.4.2 State Transition Timing Diagram
      3. 8.4.3 Power Down
      4. 8.4.4 Shutdown Mode
      5. 8.4.5 Low Power Mode (LPM)
      6. 8.4.6 Active Mode (AM)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application 1: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application 2: Driving Power at all times (PAAT) Loads With Automatic Load Wakeup and Output Bulk Capacitor Charging
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|23
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 RGE Package, 23-Pin VQFN (Transparent Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME

TPS48120-Q1

TPS48121-Q1

EN/UVLO

1

1

I

EN/UVLO input.

A voltage on this pin above V(UVLOR) 1.21V enables normal operation. If EN/UVLO is below V(UVLOF) then Gate drives are turned OFF.

Forcing this pin below V(ENF) 0.3V shuts down the device reducing quiescent current to approximately 1µA (typ). Optionally connect to the input supply through a resistive divider to set the undervoltage lockout.

When EN/UVLO is left floating an internal pull down of 100nA pulls EN/UVLO low and keeps the device in OFF state.

LPM

2

2

I

Mode control input.

When driven high, the device enters into active mode. When driven low, the devices enter into low power mode.

If low power mode is not required, LPM pin can be tied to EN/UVLO pin.

When LPM is left floating an internal pull down of 100nA pulls LPM low.

INP

3

3

I

Input signal for external FET control.

CMOS compatible input reference to GND that sets the state of GATE pin.

INP has an internal weak pull down of 100nA to GND to keep GATE pulled to SRC when INP is left floating.

I_DIR

4

4

I

Open drain I_DIR output.

This pin is asserted low by device when current through CS1+ and CS1– flows in reverse direction.

WAKE

5

5

O

Open drain WAKE output.

This pin is asserted low by device when device enters into active mode (when LPM is driven high or when a load wakeup event has occurred).

FLT

6

6

O

Open drain fault output.

FLT goes low during charge pump UVLO, Main FET SCP, I2t timer trigger, NTC based external FET overtemperature fault.

This pin asserts low after the voltage on the I2t pin has reached the fault threshold of 2V. This pin indicates the main FET is about to turn off due to an overload condition. This pin asserts low along with GATE turn off during short-circuit.

The FLT pin does not go to a high impedance state until the overcurrent condition and the auto-retry time expire.

TMR

7

7

I

Auto-retry or latch timer input after overcurrent fault.

A capacitor across TMR pin to GND sets the times for retry periods. Leave open for fastest setting.

Connect resistor across CTMR from TMR pin to GND for latch-off functionality.

GND

8

8

G

 Connect GND to system ground.

IMON

9

9

O

Analog bi-directional current monitor output.

This pin sources a scaled down ratio of current through the external current sense resistor RSNS. A resistor from this pin to GND converts current proportional to voltage.

If unused, leave floating or can be connected to ground.

ITMPO

10

10

O

Analog temperature output.

Analog voltage feedback provides a voltage proportional to thermistor temperature.

If unused, leave floating.

IOC

11

—

I

Overcurrent detection setting.

A resistor across IOC to GND sets the over current comparator threshold. IOC pin can also be driven externally using MCU.

N.C.

—

11

—

No connect.

I2t

12

—

O

I2t timer input.

A capacitor across I2t pin to GND sets the times for overcurrent (tOC).

N.C.

—

12

—

No connect.

G

13

13

O

Gate of external bypass FET.

100µA peak source and 0.39A sink capacity.

Connect to the gate of the external bypass FET.

BST

14

14

O

High side bootstrapped supply.

An external capacitor with a minimum value of 0.1µF should be connected between this pin and SRC. Voltage swing on this pin is 12V to (VIN + 12V).

SRC

15

15

O

 Source connection of the external FET.

GATE

16

16

O

High current gate driver pull-up and pull-down.

0.5A peak source and 2A sink capacity.

This pin pulls GATE up to BST and down to SRC. For the fastest tun-on and turn-off, tie this pin directly to the gate of the external high side MOSFET in main path.

TMP

18

18

I

Temperature input.

Analog connection to external NTC thermistor

Connect TMP pin directly to VS if this feature is not used
CS1–

19

19

I

 Main path current sense negative input.

Connect a resistor (RSETR) across CS1– to the external current sense resistor to set IMON gain in reverse direction.

CS1+

20

20

I

Main path current sense positive input.

Connect a resistor (RSETF) across CS1+ to the external current sense resistor to set IMON gain in forward direction.

Connect CS1+ and CS1– to VBATT if main FET current sensing is not used.

ISCP

21

21

I

Short-circuit detection threshold setting.

Connect ISCP to DRN if short-circuit protection is not desired.

VS

22

22

P

 Supply pin of the controller.

CS2–

23

23

I

Bypass path current sense negative input.

DRN

24

24

I

Main path SCP sense negative input.

Connect DRN+ and CS2– together to VBATT after RSNS if bypass path is not used.

GND

Thermal Pad

—

—

Connect exposed thermal pad to GND plane.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.