JAJSHA3K December 2012 – May 2019 TPS50301-HT
PRODUCTION DATA.
Figure 26 is a simple small signal model that can be used to understand how to design the frequency compensation. The device power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. Equation 13 shows the control to output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 25) is the power stage transconductance (gmps), which is 18 A/V for the device. The dc gain of the power stage is the product of gmps and the load resistance (RL) as shown in Equation 14 with resistive loads. As the load current increases, the dc gain decreases. This variation with load may seem problematic at first glance, but fortunately, the dominant pole moves with load current (see Equation 15). The combined effect is highlighted by the dashed line in Figure 27. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions, which makes it easier to design the frequency compensation.
where