TPS51120 Dual, Synchronous Step-Down Controller With 100-mA Standby Regulators for Notebook System Power

1 Features

3.3-V and 5-V 100-mA Bootstrapped Standby Regulators with Independent Enables
Selectable D-CAP™ Mode Enables Fast Transient Response Less than 100 ns
Selectable Low Ripple Current Mode
Less than 1% Internal Reference Accuracy
Selectable PWM-only/Auto-skip Modes
Low-side R_DS(on) Loss-less Current Sensing
R_SENSE Accurate Current Sense Option
Internal Soft-Start and Integrated V_OUT Discharge Transistors
Integrated 2-V Reference
Adaptive Gate Drivers with Integrated Boost Diode
Powergood for Each Channel with Delay Timer
Fault Disable Mode
Supply Input Voltage Range: 4.5 V to 28 V

2 Applications

Notebook Computers System Bus and I/O

3 Description

The TPS51120 is a highly sophisticated dual, synchronous step-down controller. It is a full featured controller designed to run directly off a three- or four-cell Li-ion battery and provide high-power and 5-V and/or 3.3-V standby regulation for all the downstream circuitry in a notebook computer system. High-current, 100-mA, 5-V or 3.3-V on-board linear regulators have glitch-free switch over function to SMPS and can be kept alive independently during standby state. The pseudo-constant frequency adaptive on-time control scheme supports full range of current mode operation including simplified loop compensation, ceramic output capacitors as well as seamless transition to reduced frequency operation at light-load condition. Optional D-CAP mode operation optimized for SP-CAP or POSCAP output capacitors allows further reduction of external compensation parts. Dynamic UVP supports VIN line sag without latch off by hitting 5-V UVP. No negative voltage appears at output voltage node during UVLO, UVP, and OCP, OTP or loss of VIN.

The TPS51120 32-pin QFN package is specified from –40°C to 85°C ambient temperature.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS51120	VQFN (32)	5.00 mm × 5.00 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Reference Design for D-CAP Mode Converter

4 Revision History

Changes from B Revision (Feburary 2007) to C Revision

Added Pin Configuration and Functions section, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

5 Pin Configuration and Functions

RHB Package

32-Pin VQFN

Bottom View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
COMP1	2	O	Loop compensation pin (error amplifier output). Connect RC from this pin to GND for proper loop compensation with current mode operation. Tie this pin to V5FILT for D-CAP mode operation.
COMP2	7	O
CS1	23	I	Current sense comparator input (-) for resistor sensing scheme. Or, overcurrent trip setting input for R_DS(on) current sense scheme if connected to V5FILT through the threshold setting resistor.
CS2	18	I
DRVH1	27	O	High-side MOSFET gate drive output. Source 3.5 Ω, sink 1.5 Ω, LL-node referenced floating driver. Drive voltage corresponds to VBST to LL voltage.
DRVH2	14	O
DRVL1	25	O	Rectifying (low-side) MOSFET gate drive output. Source 3.5 Ω, sink 1.5 Ω, PGND referenced driver. Drive voltage is VREG5 voltage.
DRVL2	16	O
EN1	29	I	Channel 1 and Channel 2 SMPS enable pins. Connect to 5 V to turn on with internal 3-ms soft-start. Slower soft-start is possible by applying an external capacitor from each of these pins to ground to program ramp rate.
EN2	12	I
EN3	10	I	VREG3, 3.3-V low dropout linear regulator enable pin. Connect to GND to disable. Float or tie to enabled VREG5 to turn on the regulator.
EN5	9	I	VREG5, 5-V low dropout linear regulator enable pin. Connect to GND to disable. Float or tie to VBAT to turn on the regulator.
GND	5	I	Signal ground pin.
LL1	26	I/O	High-side MOSFET gate driver return. Also serve as current sense comparator input (-) for R_DS(on) sensing, and input voltage monitor for on-time control circuitry
LL2	15	I/O
PGND1	24	I/O	Ground return for rectifying MOSFET gate driver. Connect PGND2, PGND1 and GND strongly together near the source of the rectifying FET or the GND connection of the current sense resistor. Also serve as current sense comparator input (+).
PGND2	17	I/O
PGOOD1	30	O	Power-good window comparator open drain output. Pull up with resistor to V5FILT or appropriate signal voltage. Current capability is 5-mA. PGOOD goes high 1-ms after VFB is within specified limits. Power bad (terminal goes low) is within 10 μs.
PGOOD2	11	O
SKIPSEL	32	I	Skip and fault mode selection pin. Refer to Table 5
TONSEL	31	I	On-time selection pin. Refer to Table 1 and Table 5.
V5FILT	20	I	5-V supply input for the entire control circuit. Should be provided from VREG5 via RC filter.
VBST1	28	I	Supply Input for High-side MOSFET Driver. Connect capacitor from this pin to respective LL terminal. An internal PN diode is connected between VREG5 to each of these pins. User can add external schottky diode if forward drop is critical to drive the power MOSFET.
VBST2	13	I
VFB1	3	I	SMPS feedback input. Connect the feedback resistor divider here for adjustable outputs. Tie these pins to V5FILT or for fixed output option. Refer to Table 5
VFB2	6	I
VIN	22	I	Supply Input for 5-V and 3.3-V linear regulator. Typically connected to VBAT.
VO1	1	I	These terminals serve four functions: on-time adjustment, output discharge, VREG5, VREG3 switchover input and feedback inputs for 5-V, 3.3-V fixed-output option. Connect to positive terminal of respective switch mode power supply’s output capacitor.
VO2	8	I
VREF2	4	O	2-V reference output. Capable of ±50-μA, ±2% over 0 - 85°C temperature range. Bypass to GND by 1-nF ceramic capacitor. Tie this pin to GND disables both SMPS.
VREG3	19	O	3.3-V, 100-mA low dropout linear regulator output. Bypass to PGND by 10-μF ceramic capacitor. Runs from VIN supply. Shuts off with EN3. Switches over to VO2 when 3.1 V or above is provided.
VREG5	21	O	5-V, 100-mA low dropout linear regulator output. Bypass to PGND by 10-μF ceramic capacitor. Runs from VIN supply. Internally connected to VBST and DRVL. Shuts off with EN5. Switches over to VO1 when 4.8 V or above is provided.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range unless otherwise noted⁽¹⁾

			MIN	MAX	UNIT
	Input voltage	VBST1, VBST2	–0.3	36	V
		VBST1, VBST2 wrt LL	–0.3	6
		VIN, EN5	–0.3	30
		SKIPSEL, TONSEL, EN1, EN2, CS1, CS2, V5FILT, VFB1, VFB2, EN3, VO1, VO2	–0.3	6
	Output voltage	DRVH1, DRVH2	–1	36	V
		DRVH1, DRVH2 (wrt LL)	–0.3	6
		LL1, LL2	–1	30
		VREF2, VREG3, VREG5, PGOOD1, PGOOD2, DRVL1, DRVL2, COMP1, COMP2	–0.3	6
		PGND1, PGND2	–0.3	0.3
	Source/sink current	VREF2		1	mA
		VBST		100
		VREG5, VREG3 (source only)		200
T_A	Operating ambient temperature		–40	85	°C
T_J	Junction temperature		–40	125
	Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds			255
T_stg	Storage temperature		–55	150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.

6.2 Recommended Operating Conditions

		MIN	MAX	UNIT
Input voltage, V5FILT		4.5	5.5	V
Input voltage range	VBST1, VBST2	-0.1	34	V
	VBST1, VBST2 wrt LL	-0.1	5.5
	VIN, EN5	-0.1	28
	SKIPSEL, TONSEL, EN1, EN2, CS1, CS2, V5FILT, VFB1, VFB2, EN3	-0.1	5.5
	VO1, VO2	-0.1	5.5
Output voltage range	DRVH1, DRVH2	-0.8	34	V
	DRVH1, DRVH2 (wrt LL)	-0.1	5.5
	LL1, LL2	-0.8	28
	VREF2, VREG5, VREG3, PGOOD1, PGOOD2, DRVL1, DRVL2, COMP1, COMP2	-0.1	5.5
	PGND1, PGND2	-0.1	0.1
Source/sink current	VREF2		0.08	mA
	VBST		50
	VREG5, VREF3 (source only)		100
Operating ambient temperature range, T_A		-40	85	°C

6.3 Thermal Information

THERMAL METRIC⁽¹⁾		TPS51120	UNIT
		RHB
		32 PINS
R_θJA	Junction-to-ambient thermal resistance	38.5	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.4 Electrical Characteristics

over operating free-air temperature range, V_VIN = 12 V, V_VREG5 = V_V5FILT = 5 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
SUPPLY CURRENT
I_INCCAP	Supply current	VIN current, VREG5=VREG3=No Load, EN3=EN5=FLOAT, EN1=EN2=5V, CS=5V, COMP connected to Cap	Current mode		750	1500	μA
I_INNOCAP	Supply current	VIN current, VREG5=VREG3=No Load, EN3=EN5=FLOAT; EN1=EN2=5V, CS=5V, COMP=5V	D-CAP mode		700	1400
I_IN5(STBY)	Stand-by current	VIN current, VREG5=No Load EN3=0V, EN5=FLOAT, EN1=EN2=0	5-V only		30	45
I_IN3(STBY)	Stand-by current	VIN current, VREG3=No Load EN3=FLOAT, EN5=0, EN1=EN2=0	3.3-V only		12	20
I_IN532(STBY₎	Stand-by current	VIN current, VREG5=VREG3=VREF2=No Load EN3=EN5=FLOAT, EN1=EN2=0			100	160
I_IN(SHDN)	Shut down current	VIN current, EN3=EN5=EN1=EN2=0V			10	20
VOUT and VREF2 VOLTAGES
V_OUT	Output voltage	V_FB2 = 3.3 V, T_A= 25°C, No Load		3.241	3.300	3.359	V
		V_FB2 = 3.3 V, T_A= 0 to 85°C, No Load		3.234	3.300	3.366
		V_FB2 = 3.3 V, T_A= -40 to 85°C, No Load		3.224	3.300	3.376
		V_FB1 = 5 V, T_A= 25°C, No Load		4.910	5.000	5.090
		V_FB1 = 5 V, T_A= 0 to 85°C, No Load		4.900	5.000	5.100
		V_FB1 = 5 V, T_A= -40 to 85°C, No Load		4.885	5.000	5.115
		Adjustable mode output range		1.0		5.5
V_ADJ	Output regulation voltage	Adjustable mode			1.00		V
V_{ADJ T}	Output regulation voltage tolerance	Adjustable mode, T_A= 25°C		-0.9%		0.9%
		Adjustable mode, T_A= 0 to 85°C		-1.3%		1.3%
		Adjustable mode, T_A= -40 to 85°C		-1.6%		1.6%
V_VREF2	2-V output regulation voltage	I_VREF2 ± 50 μA, T_A= 25°C		1.97	2.00	2.03	V
V_VREF2T	2-V output regulation voltage tolerance	I_VREF2 ± 50 μA, T_A= 0 to 85°C		1.96		2.04
V_VREF2T	2-V output regulation voltage tolerance	I_VREF2 ± 50 μA, T_A= -40 to 85°C		1.95		2.05
I_VFB	VFB input current	VFBx=1.02V, COMPx=open			0.02		μA
I_VFB	VFB input current	VFBx=1.02V, COMPx=5V			0.02		μA
R_DISCHARG	Discharge switch resistance	VOx=0.5V, T_A= 25°C			10	20	Ω
VREG3 VOLTAGE
V_VREG3	VREG3 Output Regulation Voltage	I_VREG3= 20 mA, 6V < VIN < 28V, T_A= 25°C		3.25	3.30	3.35	V
V_VREG3T	VREG3 Output Voltage Tolerance	I_VREG3 = 1 - 50 mA , 6V < VIN < 28V, T_A= 0 to 85°C		3.21		3.37
V_VREG3T	VREG3 Output Voltage Tolerance	I_VREG3 = 1 - 100 mA , 6V < VIN < 28V, T_A= -40 to 85°C		3.16		3.39
I_VREG3	VREG3 Output Current	T_A = 25°C, VREG3=3.14V⁽¹⁾			170		mA
V_LDO3SW	VREG3 Bootstrap Switch Threshold	Rising edge of VO2, VREG3 drops to VO2 voltage		2.85		3.10	V
V_LDO3SW	VREG3 Bootstrap Switch Threshold	Hysteresis			120		mV
R_LDO3SW	VREG3 Bootstrap Switch Resistance				1.3	3.0	Ω
VREG5 VOLTAGE
V_VREG5	VREG5 Output Regulation Voltage	I_VREG5 = 20 mA, 6V < VIN < 28V, TA= 25°C		4.925	5.00	5.075	V
V_VREG5T	VREG5 Output Voltage Tolerance	I_VREG5 = 1 - 50 mA , 6V < VIN < 28V, T_A= 0 to 85°C		4.89		5.11
		I_VREG5 = 1 - 100 mA , 6V < VIN < 28V, T_A= -40 to 85°C		4.80		5.15
I_VREG5	VREG5 Output Current	T_A= 25°C, VREG5=4.75 V⁽¹⁾			200		mA
V_LDO5SW	VREG5 Bootstrap Switch Threshold	Rising edge of VO1, VREG5 drops to VO1 voltage		4.30		4.85	V
V_LDO5SW	VREG5 Bootstrap Switch Threshold	Hysteresis			140		mV
R_LDO5SW	VREG5 Bootstrap Switch Resistance				1.3	3.0	Ω
TRANSCONDUCTANCE AMPLIFIER
Gm	Gain	T_A= 25°C			280		μS
I_COMPSINK	COMP Maximum Sink Current	VFBx=1.05V, COMPx=1.28V		8	12	16	μA
I_COMPSRC	COMP Maximum Source Current	VFBx=0.95V, COMPx=1.28V		-15	-11	-7	μA
V_COMPHI	COMP High Clamp Voltage	CSx=0V, VFBx=0.95V		1.26	1.34	1.42	V
V_COMPLO	COMP Low Clamp Voltage	CSx=0V, VFBx=1.05V		1.08	1.12	1.20	V
OUTPUT DRIVER
R_DRVH	DRVH resistance	Source, V_VBST-DRVH = 1V			3.5	7	Ω
R_DRVH	DRVH resistance	Sink, V_DRVH-LL = 1V			1.5	3
R_DRVL	DRVL resistance	Source, V_VREG5-DRVL = 1V			3.5	7
R_DRVL	DRVL resistance	Sink, V_DRVL-PGND = 1V			1.5	3
T_D	Dead time	DRVH-off to DRVL-on, T_A= 25°C			20		ns
T_D	Dead time	DRVL-off to DRVH-on, T_A= 25°C		30	60		ns
V_DTH	DRVH-off threshold	LL to GND⁽¹⁾			2		V
V_DTL	DRVL-off threshold	DRVL to GND ⁽¹⁾			1.1		V
INTERNAL BST DIODE
V_FBST	Forward Voltage	V_VREG5-VBST, I_F = 10 mA, T_A= 25°C		0.7	0.8	0.9	V
I_RBST	Reverse Current	VBST = 34 V, VREG5=5V			0.1	1.0	μA
I_BST(LEAK)	VBST Leakage current	VBST=34V, LL=28V, EN3=EN5=EN1=EN2=0V			0.1	1.0	μA
ON-TIME TIMER, INTERNAL SOFT-START and HOUSEKEEPING CLOCK
T_ON1a	On time, 5V, 180 kHz	V_LL1=12V, V_OUT1=5V, TONSEL=5V, T_A= 25°C		2150	2340	2530	ns
T_ON1b	On time, 5V, 220 kHz	V_LL1=12V, V_OUT1=5V, TONSEL=FLOAT, T_A= 25°C		1790	1950	2110
T_ON1c	On time, 5V, 280 kHz	V_LL1=12V, V_OUT1=5V, TONSEL=2V, T_A= 25°C		1370	1490	1610
T_ON1d	On time, 5V, 380 kHz	V_LL1=12V, V_OUT1=5V, TONSEL=GND, T_A= 25°C		1020	1110	1200
T_ON2a	On time, 3.3V, 270 kHz	V_LL2=12V, V_OUT2=3.3V, TONSEL=5V, T_A= 25°C		940	1030	1120
T_ON2b	On time, 3.3V, 330 kHz	V_LL2==12V, V_OUT1=3.3V, TONSEL=FLOAT, T_A= 25°C		780	850	920
T_ON2c	On time, 3.3V, 430 kHz	V_LL2==12V, V_OUT1=3.3V, TONSEL=2V, T_A= 25°C		580	650	720
T_ON2d	On time, 3.3V, 580 kHz	V_LL2==12V, V_OUT1=3.3V, TONSEL=GND, T_A= 25°C		430	480	530
T_ON(MIN)1	Minimum on time, 5V	T_A = 25°C, TONSEL=GND, V_LL1=28V, VO1=1V			70
T_ON(MIN)2	Minimum on time, 3.3V	T_A = 25°C, TONSEL=GND, V_LL2=28V, VO2=1V			45
T_OFF(MIN)	Minimum off time	T_A = 25°C, VFB=0.9V, LL=0.5V			480
T_SS	Internal Soft Start Timer	T_A = 25°C, ENx>3V			772		clks
SL_SS	Internal Soft Start Slope	T_A = 25°C, ENx>3V, Slope wrt. VFB⁽¹⁾			0.3		V/ms
F_CLK	HK clock frequency			230	290	350	kHz
UVLO/LOGIC THRESHOLD
V_ENLDOH	LDO enable threshold	EN3, EN5, low to high		0.3	0.6	0.8	V
V_ENLDOH	LDO enable threshold	Hysteresis			0.2
V_ENLDOFL3	EN3 pullup voltage	EN3 = FLOAT (OPEN)⁽¹⁾			1.7
V_ENLDOFL5	EN5 pullup voltage	EN5= FLOAT (OPEN)⁽¹⁾			3.3
I_ENLDOFL	EN3, EN5 pullup current	VENx < 0.5V			1.5	4.0	μA
V_UV(VREG5)	VREG5 UVLO threshold	Wake up		3.8	4.0	4.2	V
V_UV(VREG5)	VREG5 UVLO threshold	Hysteresis		100	200	300	mV
V_SKIPSEL	SKIPSEL threshold	Auto-SKIP Mode Enabled		0		0.7	V
		Auto-SKIP Mode Enabled, Faults Off		1.3		2.2
		PWM-Only Mode Enabled		2.7		5.5
V_TONSEL	TONSEL threshold	Fast Switching Frequency		0		0.7
		Medium Switching Frequency #2		1.3		2.2
		Medium Switching Frequency #1		2.7		3.0
		Slow Switching Frequency		4.5		5.5
I_SEL	SKIPSEL/TONSEL input current	SKIPSEL, TONSEL=0V			1	3	μA
I_SEL	SKIPSEL/TONSEL input current	SKIPSEL, TONSEL=5V			1	2	μA
V_ENSWSTAT	EN1, EN2 SS Start Voltage	BJT Base input, Switcher begins to Track ENx		0.5	0.9	1.2	V
V_ENSWEND	EN1, EN2 SS End Voltage	‘Logic High’ Level for Switcher Enable when using Internal Softstart, 0°C ≤ T_A ≤ 85°C			2.75	2.90	V
I_ENSW1,2	EN1, EN2 Pullup Current	EN1, EN2=0.6V		1	2	3	μA
V_THVFB1	VFB1 threshold	5.0V preset output			V5FILT -0.3		V
V_THVFB2	VFB2 threshold	3.3V preset output			V5FILT -0.3		V
CURRENT SENSE
V_OCL	Current limit threshold	Resistor sense scheme , V_{PGND - VCS} voltage, PGOOD=Hi		67	80	93	mV
I_TRIP	CS Sink Current	R_DS(ON) sense scheme, PGOOD=Hi, T_A= 25°C		9	10	11	μA
TC_ITRIP	I_TRIPtemperature Coefficient	R_DS(ON) sense scheme, On the basis of 25°C			4500		ppm/°C
V_OCLoff	OCP Comparator Offset	(V_VREG5-CS-V_PGND-LL) voltage, V_VREG5-CS = 80mV, R_DS(ON) sense		-10	0	10	mV
V_R(trip)	Current limit threshold setting range	V_V5FILT-V_CS voltage		30		150
V_ZC	Zero cross detection Comparator offset	V_PGNDx-V_LLx voltage, SKIPSEL=0V		-5	1	5
POWERGOOD COMPARATOR
V_TH(PG)	PGOOD Threshold	Power Bad Threshold		±7%	±10%	±13%
V_TH(PG)	PGOOD Threshold	Hysteresis			±5%
I_PG(MAX	PGOOD Sink Current	PGOOD=0.5 V		2.5	5.0		mA
T_PGDEL	PGOOD Delay Timer	Delay for PGOOD in, ‘clks’=HK Clock			256		clks
UNDERVOLTAGE and OVERVOLTAGE PROTECTION
V_OVP	VFBx OVP Trip Threshold	OVP detect		110%	115%	120%
T_OVPDEL	VFBx OVP Delay Time				2		ms
V_UVP	VFBx UVP Trip Threshold	UVP detect		65%	70%	75%
V_UVP	VFBx UVP Trip Threshold	Hysteresis			6%
T_UVPDEL	VFBx UVP Delay Timer	‘clks’=HK Clock			128		clks
THERMAL SHUTDOWN
T_SDN1	Thermal shutdown threshold	Shutdown temperature			145		°C
T_SDN1	Thermal shutdown threshold	Hysteresis			10		°C