JAJS311D February   2008  – February 2020 TPS51200

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      単純化されたDDRアプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Sink and Source Regulator (VO Pin)
      2. 7.3.2  Reference Input (REFIN Pin)
      3. 7.3.3  Reference Output (REFOUT Pin)
      4. 7.3.4  Soft-Start Sequencing
      5. 7.3.5  Enable Control (EN Pin)
      6. 7.3.6  Powergood Function (PGOOD Pin)
      7. 7.3.7  Current Protection (VO Pin)
      8. 7.3.8  UVLO Protection (VIN Pin)
      9. 7.3.9  Thermal Shutdown
      10. 7.3.10 Tracking Start-up and Shutdown
      11. 7.3.11 Output Tolerance Consideration for VTT DIMM Applications
      12. 7.3.12 REFOUT (VREF) Consideration for DDR2 Applications
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Input Voltage Applications
      2. 7.4.2 S3 and Pseudo-S5 Support
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Voltage Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 3.3-VIN, DDR2 Configuration
      2. 8.3.2 2.5-VIN, DDR3 Configuration
      3. 8.3.3 3.3-VIN, LP DDR3 or DDR4 Configuration
      4. 8.3.4 3.3-VIN, DDR3 Tracking Configuration
      5. 8.3.5 3.3-VIN, LDO Configuration
      6. 8.3.6 3.3-VIN, DDR3 Configuration with LFP
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Design Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 評価基板
        2. 11.1.2.2 SPICEモデル
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.6 Powergood Function (PGOOD Pin)

The TPS51200 device provides an open-drain PGOOD output that goes high when the VO output is within ±20% of REFOUT. PGOOD de-asserts within 10 μs after the output exceeds the size of the powergood window. During initial VO start-up, PGOOD asserts high 2 ms (typ) after the VO enters power good window. Because PGOOD is an open-drain output, a pull-up resistor with a value between 1 kΩ and 100 kΩ, placed between PGOOD and a stable active supply voltage rail is required.