JAJS311D February   2008  – February 2020 TPS51200

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      単純化されたDDRアプリケーション
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Sink and Source Regulator (VO Pin)
      2. 7.3.2  Reference Input (REFIN Pin)
      3. 7.3.3  Reference Output (REFOUT Pin)
      4. 7.3.4  Soft-Start Sequencing
      5. 7.3.5  Enable Control (EN Pin)
      6. 7.3.6  Powergood Function (PGOOD Pin)
      7. 7.3.7  Current Protection (VO Pin)
      8. 7.3.8  UVLO Protection (VIN Pin)
      9. 7.3.9  Thermal Shutdown
      10. 7.3.10 Tracking Start-up and Shutdown
      11. 7.3.11 Output Tolerance Consideration for VTT DIMM Applications
      12. 7.3.12 REFOUT (VREF) Consideration for DDR2 Applications
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Input Voltage Applications
      2. 7.4.2 S3 and Pseudo-S5 Support
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Voltage Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 3.3-VIN, DDR2 Configuration
      2. 8.3.2 2.5-VIN, DDR3 Configuration
      3. 8.3.3 3.3-VIN, LP DDR3 or DDR4 Configuration
      4. 8.3.4 3.3-VIN, DDR3 Tracking Configuration
      5. 8.3.5 3.3-VIN, LDO Configuration
      6. 8.3.6 3.3-VIN, DDR3 Configuration with LFP
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Design Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 評価基板
        2. 11.1.2.2 SPICEモデル
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.11 Output Tolerance Consideration for VTT DIMM Applications

The TPS51200 is specifically designed to power up the memory termination rail (as shown in Figure 21). The DDR memory termination structure determines the main characteristics of the VTT rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance. See Figure 22 for typical characteristics for a single memory cell.

TPS51200 v08022_lus812.gifFigure 21. Typical Application Diagram for DDR3 VTT DIMM using TPS51200
TPS51200 v08023_lus812.gifFigure 22. DDR Physical Signal System Bi-Directional SSTL Signaling

In Figure 22, when Q1 is on and Q2 is off:

  • Current flows from VDDQ via the termination resistor to VTT
  • VTT sinks current

In Figure 22, when Q2 is on and Q1 is off:

  • Current flows from VTT via the termination resistor to GND
  • VTT sources current

Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the tolerance requirement on VTT. Equation 1 applies to both DC and AC conditions and is based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003).

Equation 1. VVTTREF – 40 mV < VVTT < VVTTREF + 40 mV

The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning.

The TPS51200 ensures the regulator output voltage to be as shown in Equation 2, which applies to both DC and AC conditions.

Equation 2. VVTTREF –25 mV < VVTT < VVTTREF + 25 mV

where

  • –2 A < IVTT < 2 A

The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable to DDR, DDR2, DDR3, DDR3L, Low Power DDR3, and DDR4 applications (see Table 1 for detailed information). To meet the stability requirement, a minimum output capacitance of 20 μF is needed. Considering the actual tolerance on the MLCC capacitors, three 10-μF ceramic capacitors sufficiently meet the VTT accuracy requirement.

Table 1. DDR, DDR2, DDR3 and LP DDR3 Termination Technology

DDR DDR2 DR3 LOW POWER DDR3
FSB Data Rates 200, 266, 333, and 400 MHz 400, 533, 677, and 800 MHz 800, 1066, 1330, and 1600 MHz
Termination Motherboard termination to VTT for all signals On-die termination for data group. VTT termination for address, command and control signals On-die termination for data group. VTT termination for address, command and control signals
Termination Current Demand Maximum source/sink transient currents of up to 2.6 A to 2.9 A Not as demanding Not as demanding
Only 34 signals (address, command, control) tied to VTT Only 34 signals (address, command, control) tied to VTT
ODT handles data signals ODT handles data signals
Less than 1-A of burst current Less than 1-A of burst current
Voltage Level 2.5-V Core and
I/O 1.25-V VTT		 1.8-V Core and
I/O 0.9-V VTT		 1.5-V Core and
I/O 0.75-V VTT		 1.2-V Core and
I/O 0.6-V VTT

The TPS51200 uses transconductance (gM) to drive the LDO. The transconductance and output current of the device determine the voltage droop between the reference input and the output regulator. The typical transconductance level is 250 S at 2 A and changes with respect to the load in order to conserve the quiescent current (that is, the transconductance is very low at no load condition). The (gM) LDO regulator is a single pole system. Only the output capacitance determines the unity gain bandwidth for the voltage loop, as a result of the bandwidth nature of the transconductance (see Equation 3).

Equation 3. TPS51200 q_fugbw_slus812.gif

where

  • ƒUGBW is the unity gain bandwidth
  • gM is transconductance
  • COUT is the output capacitance

Consider these two limitations to this type of regulator that come from the output bulk capacitor requirement. In order to maintain stability, the zero location contributed by the ESR of the output capacitors must be greater than the –3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in the design. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order to prevent the gain peaking effect around the transconductance (gM) –3-dB point because of the large ESL, the output capacitor and parasitic inductance of the VO pin voltage trace.