JAJSFV8A June   2018  – December  2018 TPS51200A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      単純化されたDDRアプリケーション
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Sink and Source Regulator (VO Pin)
      2. 8.3.2 Reference Input (REFIN Pin)
      3. 8.3.3 Reference Output (REFOUT Pin)
      4. 8.3.4 Soft-Start Sequencing
      5. 8.3.5 Enable Control (EN Pin)
      6. 8.3.6 Powergood Function (PGOOD Pin)
      7. 8.3.7 Current Protection (VO Pin)
      8. 8.3.8 UVLO Protection (VIN Pin)
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 S3 and Pseudo-S5 Support
      2. 8.4.2 Tracking Startup and Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 VTT DIMM Applications
        1. 9.2.1.1 Design Parameters
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VIN Capacitor
          2. 9.2.1.2.2 VLDO Input Capacitor
          3. 9.2.1.2.3 Output Capacitor
          4. 9.2.1.2.4 Output Tolerance Consideration for VTT DIMM Applications
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design Example 1
        1. 9.2.2.1 Design Parameters
      3. 9.2.3 Design Example 2
        1. 9.2.3.1 Design Parameters
      4. 9.2.4 Design Example 3
        1. 9.2.4.1 Design Parameters
      5. 9.2.5 Design Example 4
        1. 9.2.5.1 Design Parameters
      6. 9.2.6 Design Example 5
        1. 9.2.6.1 Design Parameters
      7. 9.2.7 Design Example 6
        1. 9.2.7.1 Design Parameters
      8. 9.2.8 Design Example 7
        1. 9.2.8.1 Design Parameters
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 LDO Design Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.1.1 Design Parameters

Use the information listed in Table 1 as the design parameters.

Table 1. DDR, DDR2, DDR3, LP DDR3 and DDR4 Termination Technology and Differences

PARAMETER DDR DDR2 DR3 LP DDR3 or DDR4
FSB Data Rates 200, 266, 333 and 400 MHz 400, 533, 677 and 800 MHz 800, 1066, 1330 and 1600 MHz Same as DDR3
Termination Motherboard termination to VTT for all signals On-die termination for data group. VTT termination for address, command and control signals On-die termination for data group. VTT termination for address, command and control signals Same as DDR3
Termination Current Demand Max source/sink transient currents of up to 2.6 A to 2.9 A Not as demanding
  • Only 34 signals (address, command, control) tied to VTT
  • ODT handles data signals
Less than 1 A of burst current		 Not as demanding
  • Only 34 signals (address, command, control) tied to VTT
  • ODT handles data signals
Less than 1A of burst current		 Same as DDR3
Voltage Level 2.5-V Core and I/O 1.25-V VTT 1.8-V Core and I/O 0.9-V VTT 1.5-V Core and I/O 0.75-V VTT 1.2-V Core and I/O 0.6-V VTT