JAJSFV8A June   2018  – December  2018 TPS51200A-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      単純化されたDDRアプリケーション
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Sink and Source Regulator (VO Pin)
      2. 8.3.2 Reference Input (REFIN Pin)
      3. 8.3.3 Reference Output (REFOUT Pin)
      4. 8.3.4 Soft-Start Sequencing
      5. 8.3.5 Enable Control (EN Pin)
      6. 8.3.6 Powergood Function (PGOOD Pin)
      7. 8.3.7 Current Protection (VO Pin)
      8. 8.3.8 UVLO Protection (VIN Pin)
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 S3 and Pseudo-S5 Support
      2. 8.4.2 Tracking Startup and Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 VTT DIMM Applications
        1. 9.2.1.1 Design Parameters
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VIN Capacitor
          2. 9.2.1.2.2 VLDO Input Capacitor
          3. 9.2.1.2.3 Output Capacitor
          4. 9.2.1.2.4 Output Tolerance Consideration for VTT DIMM Applications
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design Example 1
        1. 9.2.2.1 Design Parameters
      3. 9.2.3 Design Example 2
        1. 9.2.3.1 Design Parameters
      4. 9.2.4 Design Example 3
        1. 9.2.4.1 Design Parameters
      5. 9.2.5 Design Example 4
        1. 9.2.5.1 Design Parameters
      6. 9.2.6 Design Example 5
        1. 9.2.6.1 Design Parameters
      7. 9.2.7 Design Example 6
        1. 9.2.7.1 Design Parameters
      8. 9.2.8 Design Example 7
        1. 9.2.8.1 Design Parameters
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 LDO Design Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.3 Thermal Considerations

Because the TPS51200A-Q1 device is a linear regulator, the VO current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the voltage difference between VLDOIN and VO times IO (IIO) current becomes the power dissipation as shown in Equation 2.

Equation 2. TPS51200A-Q1 q_pdiss_src_lus812.gif

In this case, if VLDOIN is connected to an alternative power supply lower than the VDDQ voltage, overall power loss can be reduced. For the sink phase, VO voltage is applied across the internal LDO regulator, and the power dissipation, PDISS_SNK can be calculated by Equation 3.

Equation 3. TPS51200A-Q1 q_pdiss_snk_lus812.gif

Because the device does not sink and source current at the same time and the IO current may vary rapidly with time, the actual power dissipation must be the time average of the above dissipations over the thermal relaxation duration of the system. Another source of power consumption is the current used for the internal current control circuitry from the VIN supply and the VLDOIN supply. This can be estimated as 5 mW or less during normal operatiing conditions. This power must be effectively dissipated from the package.

Maximum power dissipation allowed by the package is calculated by Equation 4.

PPKG = (TJ(MAX) – TA(MAX)) / RθJA
Equation 4. TPS51200A-Q1 q_p_pkg_SLUS984.gif

where

  • TJ(MAX) is 125°C
  • TA(MAX) is the maximum ambient temperature in the system
  • RθJA is the thermal resistance from junction to ambient

The thermal performance of an LDO depends on the printed circuit board (PCB) layout. The TPS51200A-Q1 device is housed in a thermally-enhanced package that has an exposed die pad underneath the body. For improved thermal performance, this die pad must be attached to ground via thermal land on the PCB. This ground trace acts as a both a heatsink and heatspreader. The typical thermal resistance, RθJA, 55.7°C/W, is achieved based on a land pattern of 3 mm × 1,9 mm with four vias (0,33-mm via diameter, the standard thermal via size) without air flow (see Figure 35).

TPS51200A-Q1 v08018_lus812.gifFigure 35. Recommend Land Pad Pattern for TPS51200A-Q1
TPS51200A-Q1 package_measure_slus812.gifFigure 36. Package Thermal Measurement

To further improve the thermal performance of this device, using a larger than recommended thermal land as well as increasing the number of vias helps lower the thermal resistance from junction to thermal pad. The typical thermal resistance from junction to thermal pad, RθJP, is 12.1°C/W (based on the recommend land pad and four standard thermal vias).