JAJSFV8A June 2018 – December 2018 TPS51200A-Q1
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 7 | I | For DDR VTT application, connect EN to SLP_S3. For any other applications, use EN as the ON/OFF function. Keep EN voltage equal or lower than VIN voltage at all times. |
GND | 8 | — | Ground. Signal ground. Connect to negative pin of the output capacitor. |
PGND(1) | 4 | — | Power ground output for the LDO |
PGOOD | 9 | O | PGOOD output. Indicates regulation. |
REFIN | 1 | I | Reference input |
REFOUT | 6 | O | Reference output. Connect to GND through 0.1-μF ceramic capacitor. If there is REFOUT capacitor at DDR side, keep the total capacitance on REFOUT pin below 1 μF. The REFOUT pin can not be open. |
VIN | 10 | I | 2.5-V or 3.3-V power supply A ceramic decoupling capacitor with a value between 1-μF and 4.7-μF is required. |
VLDOIN | 2 | I | Supply voltage for the LDO. |
VO | 3 | O | Power output for the LDO. Minimum 20-μF capacitance is required. No maximum capacitance limit. |
VOSNS | 5 | I | Voltage sense output for the LDO. Connect to positive pin of the output capacitor or the load. |