JAJSK76 September   2022 TPS51383

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation and D-CAP3 Control Mode
      2. 7.3.2  VCC LDO
      3. 7.3.3  Soft Start
      4. 7.3.4  Enable Control
      5. 7.3.5  Power Good
      6. 7.3.6  Overcurrent Protection and Undervoltage Protection
      7. 7.3.7  100-mA LDO with Switch Over
      8. 7.3.8  UVLO Protection
      9. 7.3.9  Overvoltage Protection
      10. 7.3.10 Output Voltage Discharge
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
      2. 7.4.2 Out-Of-Audio™ Mode
      3. 7.4.3 Power Save Mode (PSM)
  8. 8  Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Inductor Selection
          2. 8.2.2.1.2 Output Capacitor Selection
          3. 8.2.2.1.3 Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

MODE connected to AGND, VEN = 3.3V; TJ = –40°C to +125°C, Typical values are at TJ = 25°C and VVIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY (VIN)
VIN Input voltage range VIN 4.5 24 V
IVIN VIN Supply Current (Quiescent) VVIN = 12 V, No load, VEN = 3.3 V, non-switching 80 µA
IINSDN VIN Shutdown Current VVIN = 12 V, No load, VEN = 0 V, PG open 55 µA
UVLO
VVCC UVLO_R VCC Under-Voltage Lockout VVCC rising 4.2 4.42 V
VVCC UVLO_F VCC Under-Voltage Lockout VVCC falling 3.65 3.85 V
VVCC UVLO_H VCC Under-Voltage Lockout Hysteresis VCC voltage 450 650 mV
ENABLE (EN), MODE
VEN_R EN Threshold High-level VEN rising 1.31 1.5 V
VEN_F EN Threshold Low-level VEN falling 1.0 1.13 V
VEN_H EN Threshold Low-level Hysteresis 180 mV
IEN EN Pull down Current VEN = 0.8 V 1.3 2.3 uA
VIL;MODE Low-Level Input Voltage at MODE Pin 0.4 V
VIH;MODE High-Level Input Voltage at MODE Pin 0.8 V
IMODE MODE Pull down Current VMODE = 0.8 V 1.3 2.3 3.5 uA
VCC
VVCC VCC Output Voltage VVIN > 5.2 V, IVCC ≤ 1 mA 4.85 5 5.15 V
OUTPUT VOLTAGE (VOUT) 
VVOUT VOUT voltage (TPS51384) TJ=25°C 1.802 1.82 1.838 V
VOUT Voltage (TPS51384) -40 °C ≤ TJ  ≤125°C 1.793 1.82 1.847 V
VVOUT VOUT Voltage (TPS51383) TJ=25°C 3.326 3.36 3.394 V
VOUT Voltage (TPS51383) -40 °C ≤ TJ ≤125°C 3.30 3.36 3.42 V
DUTY CYCLE and FREQUENCY CONTROL
fSW Switching frequency CCM operation 480 600 720 kHz
tON(min) Minimum ON pulse width TJ = 25°C 65 75 ns
tOFF(min) Minimum OFF pulse width TJ = 25°C 190 ns
tOOA OOA operation period VMODE = VVCC 30 50 μs
SOFT-START
tSS Internal fixed softstart 0.55 1 1.35 ms
POWER SWITCHES (SW)
RDSON(HS) High-side MOSFET on-resistance TJ = 25°C 22 mΩ
RDSON(LS) Low-side MOSFET on-resistance TJ = 25°C 11 mΩ
BOOT CIRCUIT
CURRENT LIMIT
IOCL Low-side valley current limit Valley current limit on LS FET 9.5 11 12.5 A
INOCL Low-side negative current limit Sinking current limit on LS FET 3.9 A
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP OVP Trip Threshold 117 120 123 %
tOVPDLY OVP Prop deglitch 20 μs
tOVPDLY OVP latch-off Prop deglitch 256 μs
VUVP UVP Trip Threshold 55 60 65 %
tUVPDLY UVP Prop deglitch 256 μs
POWER GOOD (PG)
tPGDLY PG Start-Up delay PG from low to high 500 μs
tPGDLY PG delay time when VFB rising (fault) PG from high to low 20 μs
tPGDLY PG delay time when VFB falling (fault) PG from high to low 28 μs
VPGTH PG Threshold when VFB falling (fault) VFB falling (fault), percentage of VFB  79 85 89 %
VPGTH PG Threshold when VFB rising (good) VFB rising (good), percentage of VFB  86 90 94 %
VPGTH PG Threshold when VFB rising (fault) VFB rising (fault), percentage of VFB  116 120 124 %
VPGTH PG Threshold when VFB falling (good) VFB falling (good), percentage of VFB  109 115 119 %
IPGMAX PG Sink Current VPG = 0.5 V 50 mA
IPGLK PG Leak Current VPG = 5.5 V 1 μA
OUTPUT DISCHARGE
RDIS Discharge resistance TJ = 25°C, VEN = 0 V 160 Ω
SWITCH-OVER LDO OUTPUT (LDO)
VLDO LDO output voltage (TPS51383) VEN = 0 V, VIN ≥ 4.5 V 3.24 3.3 3.36 V
VLDO LDO output voltage (TPS51384) VEN = 0 V, VIN ≥ 4.5 V 1.773 1.8 1.827 V
VLOADREG LDO load regulation VEN = 0 V, ILDO = 80 mA, VIN ≥ 5.2 V -0.5 0.5 %
ILDO LDO current limit VEN = 0 V, VIN ≥ 5.2 V 100 170 240 mA
RLDOSW VOUT switch-over FET on resistance (TPS51383) VVIN ≥ 5.2 V, VEN = 3.3 V, VOUT = 3.3 V, ILDO = 50 mA 0.8 2.1 Ω
RLDOSW VOUT switch-over FET on resistance (TPS51384) VVIN ≥ 5.2 V, VEN = 3.3 V, VOUT = 1.8 V, ILDO = 50 mA 0.5 1 Ω
RLDOSW VOUT switch-over FET on resistance (TPS51383) VVIN = 4.5 V, VEN = 3.3 V, VOUT = 3.3 V, ILDO = 50 mA 1.7 2.65 Ω
RLDOSW VOUT switch-over FET on resistance (TPS51384) VVIN = 4.5 V, VEN = 3.3 V, VOUT = 1.8 V, ILDO = 50 mA 0.6 1.3 Ω
VBYPON VOUT switch-over turn on voltage VEN = 3.3 V 98 %
VBYPOFF VOUT switch-over turn off voltage VEN = 3.3 V 96 %
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold 165 °C
TJ(HYS) Thermal shutdown hysteresis (1) 20 °C
(1) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.