JAJSLU8C February   2019  – April 2021 TPS51396A

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation and D-CAP3 Control
      2. 7.3.2 Soft Start
      3. 7.3.3 Large Duty Operation
      4. 7.3.4 Power Good
      5. 7.3.5 Over Current Protection and Undervoltage Protection
      6. 7.3.6 Over Voltage Protection
      7. 7.3.7 UVLO Protection
      8. 7.3.8 Output Voltage Discharge
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Operation
      2. 7.4.2 Advanced Eco-mode Control
      3. 7.4.3 Out of Audio Mode
      4. 7.4.4 Mode Selection
      5. 7.4.5 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 1V Output Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Component Selection
          1. 8.2.2.1.1 Output Voltage Set Point
          2. 8.2.2.1.2 Inductor Selection
          3. 8.2.2.1.3 Output Capacitor Selection
          4. 8.2.2.1.4 Input Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RJE|20
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-C7DE5D25-483A-4963-839A-4084527DA2A6-low.gif Figure 5-1 RJE Package20-Pin VQFN (Top View)
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
BST 1 I Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between BST and SW, 0.1 μF is recommended.
VIN 2,3,4,5 P Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and GND.
SW 6,19,20 O Switch node terminal. Connect the output inductor to this pin.
GND 7,8,18,Pad G Power GND terminal for the controller circuit and the internal circuitry.
PGOOD 9 O Open drain power good indicator. It is asserted low if output voltage is out of PGOOD threshold, over voltage or if the device is under thermal shutdown, EN shutdown or during soft start.
SS 11 I Soft-start time selection pin. Connecting an external capacitor sets the soft-start time and if no external capacitor is connected, the soft-start time is about 1.3 ms.
NC 10,16 Not connect. Can be connected to GND plane for better thermal achieved.
EN 12 I Enable pin of buck converter. EN pin is a digital input pin, decides turn on or off buck converter. Internal pull down current to disable converter if leave this pin open.
AGND 13 G Ground of internal analog circuitry. Connect AGND to GND plane with a short trace.
FB 14 I Converter feedback input. Connect to the center tap of the resistor divider between output voltage and AGND.
MODE 15 I Llight load operation mode selection pin. Connect this pin to a resistor divider from VCC and AGND, the different MODE options are shown in Table 7-1
VCC 17 O 5.0-V internal VCC LDO output. This pin supplies voltage to the internal circuitry and gate driver. Bypass this pin with a 1-μF capacitor.