JAJSGR0F December   2010  – December 2018 TPS51916

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     アプリケーション概略
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VDDQ Switch Mode Power Supply Control
      2. 8.3.2  VREF and REFIN, VDDQ Output Voltage
      3. 8.3.3  Soft-Start and Powergood
      4. 8.3.4  Power State Control
      5. 8.3.5  Discharge Control
      6. 8.3.6  VTT and VTTREF
      7. 8.3.7  VDDQ Overvoltage and Undervoltage Protection
      8. 8.3.8  VDDQ Out-of-Bound Operation
      9. 8.3.9  VDDQ Overcurrent Protection
      10. 8.3.10 VTT Overcurrent Protection
      11. 8.3.11 V5IN Undervoltage Lockout Protection
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 MODE Pin Configuration
      2. 8.4.2 D-CAP™ Mode
    5. 8.5 D-CAP2™ Mode Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DDR3, D-CAP™ 400-kHz Application with Tracking Discharge
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
          1. 9.1.1.2.1 1. Determine the value of R1 AND R2
          2. 9.1.1.2.2 2. Choose the inductor
          3. 9.1.1.2.3 3. Choose the OCL setting resistance, RTRIP
          4. 9.1.1.2.4 Choose the output capacitors
        3. 9.1.1.3 Application Curves
      2. 9.1.2 DDR3, DCAP-2 500-kHz Application, with Tracking Discharge
        1. 9.1.2.1 Design Requirements
        2. 9.1.2.2 Detailed Design Procedure
          1. 9.1.2.2.1 Select Mode and Switching Frequency
          2. 9.1.2.2.2 Determine output capacitance
        3. 9.1.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.7 VDDQ Overvoltage and Undervoltage Protection

The TPS51916 sets the overvoltage protection (OVP) when VDDQSNS voltage reaches a level 20% (typ) higher than the REFIN voltage. When an OV event is detected, the controller changes the output target voltage to 0 V. This usually turns off DRVH and forces DRVL to be on. When the inductor current begins to flow through the low-side MOSFET and reaches the negative OCL, DRVL is turned off and DRVH is turned on, for a minimum on-time.

After the minimum on-time expires, DRVH is turned off and DRVL is turned on again. This action minimizes the output node undershoot due to LC resonance. When the VDDQSNS reaches 0 V, the driver output is latched as DRVH off, DRVL on. VTTREF and VTT are turned off and discharged using the non-tracking discharge MOSFETs regardless of the tracking mode.

The undervoltage protection (UVP) latch is set when the VDDQSNS voltage remains lower than 68% (typ) of the REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DRVH low and DRVL low and discharges the VDDQ, VTT and VTTREF outputs. UVP detection function is enabled after 1.2 ms of SMPS operation to ensure startup.

To release the OVP and UVP latches, toggle S5 or adjust the V5IN voltage down and up beyond the undervoltage lockout threshold.