JAJSGR0F December   2010  – December 2018 TPS51916

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     アプリケーション概略
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VDDQ Switch Mode Power Supply Control
      2. 8.3.2  VREF and REFIN, VDDQ Output Voltage
      3. 8.3.3  Soft-Start and Powergood
      4. 8.3.4  Power State Control
      5. 8.3.5  Discharge Control
      6. 8.3.6  VTT and VTTREF
      7. 8.3.7  VDDQ Overvoltage and Undervoltage Protection
      8. 8.3.8  VDDQ Out-of-Bound Operation
      9. 8.3.9  VDDQ Overcurrent Protection
      10. 8.3.10 VTT Overcurrent Protection
      11. 8.3.11 V5IN Undervoltage Lockout Protection
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 MODE Pin Configuration
      2. 8.4.2 D-CAP™ Mode
    5. 8.5 D-CAP2™ Mode Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DDR3, D-CAP™ 400-kHz Application with Tracking Discharge
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
          1. 9.1.1.2.1 1. Determine the value of R1 AND R2
          2. 9.1.1.2.2 2. Choose the inductor
          3. 9.1.1.2.3 3. Choose the OCL setting resistance, RTRIP
          4. 9.1.1.2.4 Choose the output capacitors
        3. 9.1.1.3 Application Curves
      2. 9.1.2 DDR3, DCAP-2 500-kHz Application, with Tracking Discharge
        1. 9.1.2.1 Design Requirements
        2. 9.1.2.2 Detailed Design Procedure
          1. 9.1.2.2.1 Select Mode and Switching Frequency
          2. 9.1.2.2.2 Determine output capacitance
        3. 9.1.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RUK Package
20-Pin QFN
Top View
TPS51916 ruk20_pinout_fiddler3.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
DRVH 14 O High-side MOSFET gate driver output.
DRVL 11 O Low-side MOSFET gate driver output.
GND 7 – Signal ground.
MODE 19 I Connect resistor to GND to configure switching frequency, control mode and discharge mode. (See Table 2)
PGND 10 – Gate driver power ground. RDS(on) current sensing input(+).
PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.
REFIN 8 I Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for stable operation.
SW 13 I/O High-side MOSFET gate driver return. RDS(on) current sensing input(–).
S3 17 I S3 signal input. (See Table 1)
S5 16 I S5 signal input. (See Table 1)
TRIP 18 I Connect resistor to GND to set OCL at VTRIP/8. Output 10-μA current at room temperature, TC = 4700 ppm/°C.
VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin.
VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF.
VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application.
VREF 6 O 1.8-V reference output.
VTT 3 O VTT 2-A LDO output. Need to connect at least 10 μF of capacitance for stability.
VTTGND 4 – Power ground for VTT LDO.
VTTREF 5 O Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability.
VTTSNS 1 I VTT output voltage feedback.
V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers.
Thermal pad – Thermal pad. Connect directly to system GND plane with multiple vias.