8.3.1 PWM Operation

The main control loop of the TPS53114 is an adaptive on-time pulse width modulation (PWM) controller using a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the high-side MOSFET is turned on. After an internal one-shot timer expires, this MOSFET is turned off. The one-shot timer is reset and the high-side MOSFET is turned back on when the feedback voltage falls below the reference voltage. The one shot is set by the converter input voltage VIN, and the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. An internal ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP mode control.

8.3.2 Drivers

The TPS53114 contains two high-current resistive MOSFET gate drivers. The low-side driver is a ground referenced, VREG5 powered driver designed to drive the gate of a high-current, low R_DS(on) N-channel MOSFET whose source is connected to PGND. The high-side driver is a floating SW referenced VBST powered driver designed to drive the gate of a high-current, low R_DS(on) N-channel MOSFET. To maintain the VBST voltage during the high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current equal to gate charge (Q_g at V_gs = 5 V) times switching frequency (f_SW).

To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF between each driver transition. During this time the inductor current is carried by one of the MOSFET's body diodes.

8.3.3 PWM Frequency and Adaptive On-time Control

TPS53114 employs adaptive on-time control scheme and does not have a dedicated on board oscillator. TPS53114 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage. Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

8.3.4 5-Volt Regulator

The TPS53114 has an internal 5-V low-dropout (LDO) Regulator to provide a regulated voltage for all both drivers and the IC's internal logic. A high-quality 4.7-μF or greater ceramic capacitor from VREG5 to GND is required to stabilize the internal regular. An internal 10-Ω resistor from VREG5 filters the regulator output to the IC's analog and logic input voltage, V5FILT. An additional high-quality 1.0-μF ceramic capacitor is required from V5FILT to GND to filter switching noise from VREG5.

8.3.5 Soft Start

The TPS53114 has a programmable soft start . When the EN pin becomes high, 2.0-μA current begins charging the capacitor which is connected SS pin to GND. Smooth control of the output voltage is maintained during start up.

8.3.6 Pre-bias Support

The TPS53114 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the low-side driver is held off until the soft start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage (VFB)), then the TPS53114 slowly activates synchronous rectification by limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the pre-bias output, and ensure that the output voltage (V_OUT) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal mode operation.

8.3.7 Switching Frequency Selection

The TPS53114 allows the user to select from two different switching frequencies by connecting the FSEL pin to either GND or V5FILT. Connect FSEL to GND for a switching frequency (f_sw) of 350 KHz. Connect FSEL to V5FILT for a switching frequency of 700 KHz.

8.3.8 Output Discharge Control

The TPS53114 discharges the outputs when EN is low, or the controller is turned off by the protection functions (OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40-Ω MOSFET which is connected to VO and PGND. The external low-side MOSFET is not turned on during the output discharge operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that, on start, the regulated voltage always initializes from 0 V.

8.3.9 Over Current Protection

TPS53114 has a cycle-by-cycle over current limit feature. The over current limits the inductor valley current by monitoring the voltage drop across the low-side MOSFET R_DS(on) during the low-side driver on-time. If the inductor current is larger than the over current limit (OCL), the TPS53114 delays the start of the next switching cycle until the sensed inductor current falls below the OCL current. MOSFET R_DS(on) current sensing is used to provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIP pin should be connected to GND through a trip voltage setting resistor, according to Equation 1 and Equation 2.

Equation 1.

Equation 2.

The trip voltage should be between 30 mV to 200 mV over all operational temperature, including the
4000 ppm/°C temperature slope compensation for the temperature dependency of the R_DS(on). If the load current exceeds the over current limit, the voltage will begin to drop. If the over current conditions continues, the output voltage will fall below the under voltage protection threshold and the TPS53114 will shut down.

8.3.10 Over/under Voltage Protection

TPS53114 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage is higher than 115% of the reference voltage, the OVP comparator output goes high and the circuit latches the high-side MOSFET driver OFF and the low-side MOSFET driver ON. When the feedback voltage is lower than 70% of the reference voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 30 μs, TPS53114 latches OFF both top and bottom MOSFET drivers. This function is enabled approximately 1.7x T_SS after power-on. The OVP and UVP latch off is reset when EN goes low level.

8.3.11 UVLO Protection

TPS53114 has V5FILT under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin. When the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF and output discharge is ON. The UVLO is non-latch protection.

8.3.12 Thermal Shutdown

The TPS53114 includes an over temperature protection shut-down feature. If the TPS53114 die temperature exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal shutdown is a non-latch protection.

8.4.1 Operation

The TPS53114 has two operating modes. The TPS53114 is in shut down mode when the EN pin is low. When the EN pin is pulled high, the TPS53114 enters the normal operating mode.