JAJSE87A December   2017  – March 2019 TPS53119

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Soft-Start
      2. 7.3.2  Adaptive ON-Time D-CAP Control and Frequency Selection
      3. 7.3.3  Small Signal Model
      4. 7.3.4  Ramp Signal
      5. 7.3.5  Adaptive Zero Crossing
      6. 7.3.6  Output Discharge Control
      7. 7.3.7  Low-Side Driver
      8. 7.3.8  High-Side Driver
      9. 7.3.9  Power Good
      10. 7.3.10 Current Sense and Overcurrent Protection
      11. 7.3.11 Overvoltage and Undervoltage Protection
      12. 7.3.12 UVLO Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Condition in Auto-Skip Operation
      2. 7.4.2 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application With Power Block
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 External Components Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application With Ceramic Output Capacitors
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Parts Selection With All Ceramic Output Capacitors
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.10 Current Sense and Overcurrent Protection

TPS53119 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the period in that the inductor current is larger than the overcurrent trip level. In order to provide both good accuracy and cost-effective solution, TPS53119 supports temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor, RTRIP. The TRIP terminal sources ITRIP current, which is 10 µA typically at room temperature, and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 6.

NOTE

The VTRIP is limited up to approximately 3 V internally.
Equation 6. TPS53119 q_vtrip_lusaa8.gif

The inductor current is monitored by the voltage between GND pin and SW pin so that SW pin should be connected to the drain terminal of the low-side MOSFET properly. ITRIP has 4700-ppm/°C temperature slope to compensate the temperature dependency of the RDS(on). The GND pin is used as the positive current-sensing node. The GND pin should be connected to the proper current sensing device, (for example, the source terminal of the low-side MOSFET.)

As the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 7.

Equation 7. TPS53119 q_iocp_lusaa8.gif

In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down. After a hiccup delay (16 ms with 0.7-ms sort start), the controller restarts. If the overcurrent condition remains, the procedure is repeated and the device enters hiccup mode.

During the CCM, the negative current limit (NCL) protects the external FET from carrying too much current. The NCL detect threshold is set as the same absolute value as positive OCL but negative polarity.

NOTE

The threshold still represents the valley value of the inductor current.