SLUS825C February   2008  – August 2014 TPS53124

PRODUCTION DATA.  

  1. 1Simplified Schematics
  2. 2Pin Configuration and Functions
  3. 3Specifications
    1. 3.1 Absolute Maximum Ratings
    2. 3.2 Handling Ratings
    3. 3.3 Recommended Operating Conditions
    4. 3.4 Thermal Information
    5. 3.5 Electrical Characteristics
    6. 3.6 Typical Characteristics
  4. 4Detailed Description
    1. 4.1 Overview
    2. 4.2 Functional Block Diagram
    3. 4.3 Feature Description
      1. 4.3.1  PWM Operation
      2. 4.3.2  Low-Side Driver
      3. 4.3.3  High-Side Driver
      4. 4.3.4  PWM Frequency and Adaptive On-Time Control
      5. 4.3.5  Soft Start
      6. 4.3.6  Output Discharge Control
      7. 4.3.7  Current Protection
      8. 4.3.8  Over/Under Voltage Protection
      9. 4.3.9  UVLO Protection
      10. 4.3.10 Thermal Shutdown
    4. 4.4 Device Functional Modes
  5. 5Application and Implementation
    1. 5.1 Application Information
    2. 5.2 Typical Application
      1. 5.2.1 Design Requirements
      2. 5.2.2 Detailed Design Procedure
        1. 5.2.2.1 Choose Inductor
        2. 5.2.2.2 Loop Compensation and External Parts Selection
        3. 5.2.2.3 Choose Input Capacitor
        4. 5.2.2.4 Choose Bootstrap Capacitor
        5. 5.2.2.5 Choose VREG5 and V5FILT Capacitor
        6. 5.2.2.6 Choose Output Voltage Set Point Resistors
        7. 5.2.2.7 Choose Over Current Set Point Resistor
        8. 5.2.2.8 Choose Soft Start Capacitor
      3. 5.2.3 Application Curves (QFN)
  6. 6Power Supply Recommendations
  7. 7Layout
    1. 7.1 Layout Guidelines
    2. 7.2 Layout Example
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Layout

7.1 Layout Guidelines

  • Keep the input switching current loop as small as possible. (VIN ≥ C3 ≥ PNGD ≥ Sync FET ≥ SW ≥ Control FET)
  • Place the input capacitor (C3) close to the top switching FET. The output current loop should also be kept as small as possible.
  • Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback terminal (FBx) of the device.
  • Keep analog and non-switching components away from switching components.
  • Make a single point connection from the signal ground to power ground.
  • Do not allow switching current to flow under the device.
  • DRVH and DRVL line should not run close to SW node or minimize it.
  • GND terminals for capacitors of SSx and V5FILT and resistors of feedback and TRIPx should be connected to SGND.
  • GND terminals for capacitors of VREG5 and VIN should be connected to PGND.
  • Signal lines should not run under/near output inductor or minimize it.

7.2 Layout Example

layout_ds_a_slus825.gifFigure 15. Layout Example for QFN