JAJSGZ2B DECEMBER   2011  – February 2019 TPS53219A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Soft-Start
      2. 7.3.2  Adaptive ON-Time D-CAP Control and Frequency Selection
      3. 7.3.3  Small Signal Model
      4. 7.3.4  Ramp Signal
      5. 7.3.5  Adaptive Zero Crossing
      6. 7.3.6  Output Discharge Control
      7. 7.3.7  Low-Side Driver
      8. 7.3.8  High-Side Driver
      9. 7.3.9  Power Good
      10. 7.3.10 Current Sense and Overcurrent Protection
      11. 7.3.11 Overvoltage and Undervoltage Protection
      12. 7.3.12 UVLO Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Condition in Auto-Skip Operation
      2. 7.4.2 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application With Power Block
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External Components Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application With Ceramic Output Capacitors
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Parts Selection With All Ceramic Output Capacitors
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 Small Signal Model

From small-signal loop analysis, a buck converter using D-CAP mode can be simplified as shown in Figure 17.

TPS53219A v11277_lusau4.gifFigure 17. Simplified Modulator Model

The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity). The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially constant.

Equation 1. TPS53219A q_hs_lusaa8.gif

For the loop stability, the 0-dB frequency, ƒ0, defined below must be lower than ¼ of the switching frequency.

Equation 2. TPS53219A q_f0_lusaa8.gif

According to Equation 2, the loop stability of D-CAP mode modulator is mainly determined by the capacitor chemistry. For example, specialty polymer capacitors (SP-CAP) have an output capacitance on the order of several 100 µF and ESR in range of 10 mΩ. These yields an f0 on the order of 100 kHz or less and a more stable loop. However, ceramic capacitors have an ƒ0 at more than 700 kHz, and require special care when used with this modulator. An application circuit for ceramic capacitor is described in section External Parts Selection With All Ceramic Output Capacitors.