JAJSGZ2B DECEMBER   2011  – February 2019 TPS53219A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Soft-Start
      2. 7.3.2  Adaptive ON-Time D-CAP Control and Frequency Selection
      3. 7.3.3  Small Signal Model
      4. 7.3.4  Ramp Signal
      5. 7.3.5  Adaptive Zero Crossing
      6. 7.3.6  Output Discharge Control
      7. 7.3.7  Low-Side Driver
      8. 7.3.8  High-Side Driver
      9. 7.3.9  Power Good
      10. 7.3.10 Current Sense and Overcurrent Protection
      11. 7.3.11 Overvoltage and Undervoltage Protection
      12. 7.3.12 UVLO Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Light Load Condition in Auto-Skip Operation
      2. 7.4.2 Forced Continuous Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application With Power Block
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External Components Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Application With Ceramic Output Capacitors
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 External Parts Selection With All Ceramic Output Capacitors
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

RGT Package
16-Pin QFN With Exposed Thermal Pad
Top View
TPS53219A pinout_rgt16_lusau4.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
DRVH 13 O High-side MOSFET driver output. The SW node referenced floating driver. The gate drive voltage is defined by the voltage across VBST to SW node bootstrap flying capacitor.
DRVL 11 O Synchronous MOSFET driver output. The PGND referenced driver. The gate drive voltage is defined by VDRV voltage.
EN 2 I Enable pin. Place a 1-kΩ resistor in series with this pin if the source voltage is higher than 5.5 V.
GND 7 G Ground pin. This is the ground of internal analog circuitry. Connect to GND plane at single point.
MODE 5 I Soft-start and skip/CCM selection. Connect a resistor to select soft-start time using Table 1. The soft-start time is detected and stored into internal register during start-up.
NC 15 – No connection.
PAD – – Thermal pad. Use five vias to connect to GND plane.
PGOOD 16 O Open-drain power good flag. Provides 1-ms start-up delay after the VFB pin voltage falls within specified limits. When VFB goes out specified limits PGOOD goes low after a 2-µs delay.
PGND 8 G Power ground. Connect to GND plane.
RF 4 I Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using Table 2. The switching frequency is detected and stored during the start-up.
SW 12 P Output of converted power. Connect this pin to the output inductor.
TRIP 1 I OCL detection threshold setting pin. 10 µA at room temp, 4700 ppm/°C current is sourced and set the OCL trip voltage as follows.
VOCL = VTRIP/8 spacer ( VTRIP ≤ 3 V, VOCL ≤ 375 mV)
VBST 14 P Supply input for high-side FET gate driver (boost terminal). Connect a capacitor from this pin to SW-node. Internally connected to VREG through bootstrap MOSFET switch.
VDD 6 P Controller power supply input. The input range is from 4.5 V to 25 V.
VDRV 10 I Gate drive supply voltage input. Connect to VREG if using LDO output as gate drive supply.
VFB 3 I Output feedback input. Connect this pin to VOUT through a resistor divider.
VREG 9 O 6.2-V LDO output. This is the supply of internal analog circuitry and driver circuitry.
(1) I=Input, O=Output, P=Power, G=Ground