SLUSAK4D June   2011  – July 2015 TPS53317

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation
      2. 7.3.2 PWM Frequency and Adaptive On-Time Control
      3. 7.3.3 Light-Load Power Saving Features
      4. 7.3.4 Power Sequences
        1. 7.3.4.1 Non-Tracking Startup
        2. 7.3.4.2 Tracking Startup
      5. 7.3.5 Protection Features
        1. 7.3.5.1 5-V Undervoltage Protection (UVLO)
        2. 7.3.5.2 Power Good Signals
        3. 7.3.5.3 Output Overvoltage Protection (OVP)
        4. 7.3.5.4 Output Undervoltage Protection (UVP)
        5. 7.3.5.5 Overcurrent Protection
          1. 7.3.5.5.1 Overcurrent Limit
          2. 7.3.5.5.2 Negative OCL
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Non-Droop Configuration
      2. 7.4.2 Droop Configuration
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 DDR4 SDRAM Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Step 1. Determine Configuration
          2. 8.2.1.2.2 Step 2. Select Inductor
          3. 8.2.1.2.3 Step 3. Determine Output Capacitance
          4. 8.2.1.2.4 Step 4. Input Capacitance
          5. 8.2.1.2.5 Step 5. Compensation Network
          6. 8.2.1.2.6 Peripheral Component Selection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DDR3 SDRAM Application
        1. 8.2.2.1 Design Requirements
      3. 8.2.3 Non-Tracking Point-of-Load (POL) Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

1 Features

  • TI proprietary Integrated MOSFET and Packaging Technology
  • Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current
  • External Tracking
  • Minimum External Components Count
  • 1-V to 6-V Conversion Voltage
  • D-CAP+™ Mode Architecture
  • Supports All MLCC Output Capacitors and SP/POSCAP
  • Selectable SKIP Mode or Forced CCM
  • Optimized Efficiency at Light and Heavy Loads
  • Selectable 600-kHz or 1-MHz Switching Frequency
  • Selectable Overcurrent Limit (OCL)
  • Overvoltage, Over-Temperature and Hiccup Undervoltage Protection
  • Adjustable Output Voltage from 0.6 V to 2 V
  • 3.5 mm × 4 mm, 20-Pin VQFN Package

2 Applications

  • Memory Termination Regulator for DDR, DDR2, DDR3, DDR3L, and DDR4
  • VTT Termination
  • Low-Voltage Applications for 1-V to 6-V Input Rails

3 Description

The TPS53317 device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with both sink and source capability. The TPS53317 device employs D-CAP+™ mode operation that provides ease of use, low external component count and fast transient response. The device can also be used for other point-of-load (POL) regulation applications requiring up to 6 A. In addition, the device supports full, 6-A, output sinking current capability with tight voltage regulation.

The device features two switching frequency settings (600 kHz and 1 MHz), integrated droop support, external tracking capability, pre-bias startup, output soft discharge, integrated bootstrap switch, power good function, V5IN pin UVLO protection, and supports both ceramic and SP/POSCAP capacitors. It supports input voltages up to 6.0 V, and output voltages adjustable from 0.6 V to 2.0 V.

The TPS53317 device is available in the 3.5 mm × 4 mm, 20-pin, VQFN package (Green RoHs compliant and Pb free) with TI proprietary Integrated MOSFET and packaging technology and is specified from –40°C to 85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS53317 VQFN (20) 3.50 mm × 4.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Application

TPS53317 v11105x_slusak4.gif