7.3.4.1 D-CAP3 Mode

From small-signal loop analysis, a buck converter using the D-CAP3 mode control architecture can be simplified as shown in Figure 35.

Figure 35. D-CAP3 Mode

The D-CAP3 control architecture includes an internal ripple generation network enabling the use of very low-ESR output capacitors such as multilayered ceramic capacitors (MLCC). No external current sensing network or voltage compensators are required with D-CAP3 control architecture. The role of the internal ripple generation network is to emulate the ripple component of the inductor current information and then combine it with the voltage feedback signal to regulate the loop operation. For any control topologies supporting no external compensation design, there is a minimum and/or maximum range of the output filter it can support. The output filter used with the TPS53513 device is a lowpass L-C circuit. This L-C filter has double pole that is described in Equation 2.

Equation 2.

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS53513 device. The low frequency L-C double pole has a 180 degree in phase. At the output filter frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per decade and increases the phase to 90 degree one decade above the zero frequency.

The inductor and capacitor selected for the output filter must be such that the double pole of Equation 2 is located close enough to the high-frequency zero so that the phase boost provided by the high-frequency zero provides adequate phase margin for the stability requirement.

After identifying the application requirements, the output inductance should be designed so that the inductor peak-to-peak ripple current is approximately between 25% and 35% of the I_CC(max) (peak current in the application). Use Table 2 to help locate the internal zero based on the selected switching frequency. In general, where reasonable (or smaller) output capacitance is desired, Equation 3 can be used to determine the necessary output capacitance for stable operation.

Equation 3.

If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design. For example, when using an MLCC with specifications of 10-µF, X5R and 6.3 V, the deratings by DC bias and AC bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this case is 40% and 4-µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be used in the system/applications.

Table 3 shows the recommended output filter range for an application design with the following specifications:

• Input voltage, V_IN = 12 V
• Switching frequency, f_SW = 600 kHz
• Output current, I_OUT = 8 A

The minimum output capacitance is verified by the small-signal measurement conducted on the EVM using the following two criteria:

• Loop crossover frequency is less than one-half the switching frequency (300 kHz)
• Phase margin at the loop crossover is greater than 50 degrees

For the maximum output capacitance recommendation, simplify the procedure to adopt an unrealistically high output capacitance for this type of converter design, then verify the small-signal response on the EVM using the following one criteria:

• Phase margin at the loop crossover is greater than 50 degrees

As indicated by the phase margin, the actual maximum output capacitance (C_OUT(max)) can continue to go higher. However, small-signal measurement (bode plot) should be done to confirm the design.

Select a MODE pin configuration as shown in Table 4 to in double the R-C time-constant option for the maximum output capacitance design and application. Select a MODE pin configuration to use single R-C time constant option for the normal (or smaller) output capacitance design and application.

The MODE pin also selects skip-mode or FCCM-mode operation.

For higher output voltage at or above 2.0 V, additional phase boost might be required to secure sufficient phase margin due to phase delay/loss for higher output voltage (large on-time (t_ON)) setting in a fixed on time topology based operation.

A feedforward capacitor placing in parallel with R_UPPER is found to be very effective to boost the phase margin at loop crossover. Refer to TI application note SLVA289 for details.