JAJSC06C SEPTEMBER   2013  – June 2018 TPS53513

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  5-V LDO and VREG Start-Up
      2. 7.3.2  Enable, Soft Start, and Mode Selection
      3. 7.3.3  Frequency Selection
      4. 7.3.4  D-CAP3 Control and Mode Selection
        1. 7.3.4.1 D-CAP3 Mode
        2. 7.3.4.2 Sample and Hold Circuitry
        3. 7.3.4.3 Adaptive Zero-Crossing
      5. 7.3.5  Power-Good
      6. 7.3.6  Current Sense and Overcurrent Protection
      7. 7.3.7  Overvoltage and Undervoltage Protection
      8. 7.3.8  Out-Of-Bounds Operation
      9. 7.3.9  UVLO Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Choose the Switching Frequency
        2. 8.2.2.2 Choose the Operation Mode
        3. 8.2.2.3 Choose the Inductor
        4. 8.2.2.4 Choose the Output Capacitor
        5. 8.2.2.5 Determine the Value of R1 and R2
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Performance
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1 Layout Guidelines

Before beginning a design using the TPS53513 device, consider the following:

  • Place the power components (including input and output capacitors, the inductor, and the DPA02259 device) on the solder side of the PCB. To shield and isolate the small signal traces from noisy power lines, insert and connect at least one inner plane to ground.
  • All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE, and RF must be placed away from high-voltage switching nodes such as SW and VBST to avoid coupling. Use internal layers as ground planes and shield the feedback trace from power traces and components.
  • GND (pin 22) must be connected directly to the thermal pad. Connect the thermal pad to the PGND terminals and then to the GND plane.
  • The GND1 terminal (pin 27) and the GND2 terminal (pin 28) are not actual GND terminals and neither of these terminals should be used for dedicated ground connection. The recommendation is to connect GND1 terminal (pin 27) and the GND2 terminal (pin 28) to the nearby ground.
  • Place the VIN decoupling capacitors as close to the VIN and PGND terminals as possible to minimize the input AC-current loop.
  • Place the feedback resistor near the device to minimize the VFB trace distance.
  • Place the frequency-setting resistor (RRF), OCP-setting resistor (RTRIP) and mode-setting resistor (RMODE) close to the device. Use the common GND via to connect the resistors to the GND plane if applicable.
  • Place the VDD and VREG decoupling capacitors as close to the device as possible. Provide GND vias for each decoupling capacitor and ensure the loop is as small as possible.
  • This design defines the PCB trace as a switch node, which connects the SW terminals and high-voltage side of the inductor. The switch node should be as short and wide as possible.
  • Use separated vias or trace to connect SW node to the snubber, bootstrap capacitor, and ripple-injection resistor. Do not combine these connections.
  • Place one more small capacitor (2.2-nF, 0402 size) between the VIN and PGND terminals. This capacitor must be placed as close to the device as possible.
  • TI recommends placing a snubber between the SW shape and GND shape for effective ringing reduction. The value of snubber design starts at 3 Ω + 470 pF.
  • Consider R-C-CC network (ripple injection network) component placement and place the AC coupling capacitor, CC, close to the device, and R and C close to the power stage. (Application designs with output capacitance lower than the minimum may require only an R‐C‐C network. In this case, Bode plot verification is needed to validate the design).
  • See Figure 56 for the layout recommendation.