SLUSCJ3A April   2016  – June 2016 TPS53632G

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Timing Requirements
  8. 8 Switching Characteristics
  9. 9 Typical Characteristics (Half-Bridge Operation)
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Current Sensing
      2. 10.3.2  Load Transients
      3. 10.3.3  PWM and SKIP Signals
      4. 10.3.4  5-V, 3.3-V and 1.8-V Undervoltage Lockout (UVLO)
      5. 10.3.5  Output Undervoltage Protection (UVP)
      6. 10.3.6  Overcurrent Protection (OCP)
      7. 10.3.7  Overvoltage Protection
      8. 10.3.8  Analog Current Monitor, IMON and Corresponding Digital Output Current
      9. 10.3.9  Addressing
      10. 10.3.10 I2C Interface Operation
        1. 10.3.10.1 Key for Protocol Examples
        2. 10.3.10.2 Protocol Examples
      11. 10.3.11 Start-Up Sequence
      12. 10.3.12 Power Good Operation
      13. 10.3.13 Fault Behavior
    4. 10.4 Device Functional Modes
      1. 10.4.1 PWM Operation
    5. 10.5 Configuration and Programming
      1. 10.5.1 Operating Frequency
      2. 10.5.2 Overcurrent Protection (OCP) Level
      3. 10.5.3 IMON Gain
      4. 10.5.4 Slew Rate
      5. 10.5.5 Base Address
      6. 10.5.6 Ramp Selection
      7. 10.5.7 Active Phases
    6. 10.6 Register Maps
      1. 10.6.1 Voltage Select Register (VSR) (00h)
      2. 10.6.2 IMON Register (03h)
      3. 10.6.3 VMAX Register (04h)
      4. 10.6.4 Power State Register (06h)
      5. 10.6.5 SLEW Register (07h)
      6. 10.6.6 Lot Code Registers (10-13h)
      7. 10.6.7 Fault Register (14h)
  11. 11Applications and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 D-CAP+™ Half-Bridge Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
          1. 11.2.1.2.1 Step 1: Select Switching Frequency
          2. 11.2.1.2.2 Step 2: Set The Slew Rate
          3. 11.2.1.2.3 Step 3: Determine Inductor Value And Choose Inductor
          4. 11.2.1.2.4 Step 4: Determine Current Sensing Method
          5. 11.2.1.2.5 Step 5: DCR Current Sensing
          6. 11.2.1.2.6 Step 6: Select OCP Level
          7. 11.2.1.2.7 Step 7: Set the Load-Line Slope
          8. 11.2.1.2.8 Step 8: Current Monitor (IMON) Setting
        3. 11.2.1.3 Application Performance Plots
        4. 11.2.1.4 Loop Compensation for Zero Load-Line
  12. 12Power Supply Recommendations
  13. 13 Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 PCB Layout
      2. 13.1.2 Current Sensing Lines
      3. 13.1.3 Feedback Voltage Sensing Lines
      4. 13.1.4 PWM And SKIP Lines
        1. 13.1.4.1 Minimize High Current Loops
      5. 13.1.5 Power Chain Symmetry
      6. 13.1.6 Component Location
      7. 13.1.7 Grounding Recommendations
      8. 13.1.8 Decoupling Recommendations
      9. 13.1.9 Conductor Widths
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Trademarks
    2. 14.2 Electrostatic Discharge Caution
    3. 14.3 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Power Supply Recommendations

This device is designed to operate from a supply voltage at the V5A pin (5-V power input for analog circuits) from 4.5 V to 5.5 V and a supply voltage at the VDD pin (3.3-V digital power input) from 3.1 V to 3.5 V, and a supply voltage at the VINTF pin from 1.7 V to 3.5 V. Use only a well-regulated supply. The VIN pin input must be connected to the conversion input voltage and must not exceed 28 V. Proper bypassing of the V5A and VDD input supplies is critical for noise performance, as is PCB layout and grounding scheme. See the recommendations in the Layout section.