SLUSCJ3A April   2016  – June 2016 TPS53632G

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Timing Requirements
  8. 8 Switching Characteristics
  9. 9 Typical Characteristics (Half-Bridge Operation)
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Current Sensing
      2. 10.3.2  Load Transients
      3. 10.3.3  PWM and SKIP Signals
      4. 10.3.4  5-V, 3.3-V and 1.8-V Undervoltage Lockout (UVLO)
      5. 10.3.5  Output Undervoltage Protection (UVP)
      6. 10.3.6  Overcurrent Protection (OCP)
      7. 10.3.7  Overvoltage Protection
      8. 10.3.8  Analog Current Monitor, IMON and Corresponding Digital Output Current
      9. 10.3.9  Addressing
      10. 10.3.10 I2C Interface Operation
        1. 10.3.10.1 Key for Protocol Examples
        2. 10.3.10.2 Protocol Examples
      11. 10.3.11 Start-Up Sequence
      12. 10.3.12 Power Good Operation
      13. 10.3.13 Fault Behavior
    4. 10.4 Device Functional Modes
      1. 10.4.1 PWM Operation
    5. 10.5 Configuration and Programming
      1. 10.5.1 Operating Frequency
      2. 10.5.2 Overcurrent Protection (OCP) Level
      3. 10.5.3 IMON Gain
      4. 10.5.4 Slew Rate
      5. 10.5.5 Base Address
      6. 10.5.6 Ramp Selection
      7. 10.5.7 Active Phases
    6. 10.6 Register Maps
      1. 10.6.1 Voltage Select Register (VSR) (00h)
      2. 10.6.2 IMON Register (03h)
      3. 10.6.3 VMAX Register (04h)
      4. 10.6.4 Power State Register (06h)
      5. 10.6.5 SLEW Register (07h)
      6. 10.6.6 Lot Code Registers (10-13h)
      7. 10.6.7 Fault Register (14h)
  11. 11Applications and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 D-CAP+™ Half-Bridge Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
          1. 11.2.1.2.1 Step 1: Select Switching Frequency
          2. 11.2.1.2.2 Step 2: Set The Slew Rate
          3. 11.2.1.2.3 Step 3: Determine Inductor Value And Choose Inductor
          4. 11.2.1.2.4 Step 4: Determine Current Sensing Method
          5. 11.2.1.2.5 Step 5: DCR Current Sensing
          6. 11.2.1.2.6 Step 6: Select OCP Level
          7. 11.2.1.2.7 Step 7: Set the Load-Line Slope
          8. 11.2.1.2.8 Step 8: Current Monitor (IMON) Setting
        3. 11.2.1.3 Application Performance Plots
        4. 11.2.1.4 Loop Compensation for Zero Load-Line
  12. 12Power Supply Recommendations
  13. 13 Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 PCB Layout
      2. 13.1.2 Current Sensing Lines
      3. 13.1.3 Feedback Voltage Sensing Lines
      4. 13.1.4 PWM And SKIP Lines
        1. 13.1.4.1 Minimize High Current Loops
      5. 13.1.5 Power Chain Symmetry
      6. 13.1.6 Component Location
      7. 13.1.7 Grounding Recommendations
      8. 13.1.8 Decoupling Recommendations
      9. 13.1.9 Conductor Widths
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Trademarks
    2. 14.2 Electrostatic Discharge Caution
    3. 14.3 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage V5A –0.3 6.0 V
VBUS –0.3 30.0
VDD –0.3 3.6
COMP, CSP1, CSP2, CSN1, CSN2, DROOP, EN, FREQ-P, IMON, OCP-I, O-USR, RAMP, SCL, SDA, SLEWA, VFB, VINTF, VREF –0.3 3.6
GFB –0.2 0.2
Output voltage PGOOD –0.3 3.6 V
PWM-LO, PWM-HI, SKIP –0.3 6.0
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM) ESD stress voltage(1) ±2000 V
Charged device model (CDM) ESD stress voltage(2) ±750 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VI Input voltage V5A 4.5 5.5 V
VBUS –0.1 28
VDD 3.1 3.5
CSN1, CSN2, CSP1, CSP2, IMON, OCP-I, O-USR, RAMP, SCL, SDA, VFB, VINTF, VREF –0.1 3.5
COMP, DROOP, EN, FREQ-P, SLEWA –0.1 5.5
GFB –0.1 0.1
VO Output voltage PGOOD –0.1 3.5 V
PWM-LO, PWM-HI, SKIP –0.1 5.5
TA Operating ambient temperature –10 105 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS53632G UNITS
RSM (VQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance 37.2 °C/W
RθJCtop Junction-to-case (top) thermal resistance 31.9 °C/W
RθJB Junction-to-board thermal resistance 8.1 °C/W
RψJT Junction-to-top characterization parameter 0.4 °C/W
RψJB Junction-to-board characterization parameter 7.9 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 2.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended free-air temperature range, VV5A = 5.0 V, VVDD = 3.3 V, VGFB = GND, VVFB = VCORE (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY: CURRENTS, UVLO AND POWER-ON-RESET
IV5-3P V5A supply current VDAC < VVFB < (VDAC + 100 mV), EN = ‘HI’ 3.6 6.0 mA
IVDD-3P VDD supply current VDAC < VVFB < (VDAC + 100 mV), EN = ‘HI’, digital buses idle 0.2 0.8
IV5STBY V5A standby current EN = ‘LO’ 125 200 µA
IVDDSTBY VDD standby current EN = ‘LO’ 23 40
IVDD-1P8 VINTF supply current All conditions, digital buses idle 1.7 5.0
VUVLOH V5A UVLO ‘OK’ threshold VVFB < 200 mV, Ramp up, VVDD > 3 V, EN = ’HI’, switching begins. 4.2 4.4 4.52 V
VUVLOL V5A UVLO fault threshold Ramp down, EN = ’HI’, VVDD > 3 V, VVFB = 100 mV, restart if 5-V falls below VPOR then rises > VUVLOH, or EN is toggled w/ VV5A > VUVLOH 4.00 4.2 4.35
VPOR V5A fault latch reset threshold Ramp down, EN = ‘HI’, VVDD > 3 V. Can restart if 5-V rises to VUVLOH and no other faults present. 1.2 1.9 2.5
V3UVLOH VDD UVLO ‘OK’ threshold VVFB < 200 mV. Ramp up, VV5A > 4.5 V, EN = ’HI’, Switching begins. 2.5 2.8 3.0
V3UVLOL Fault threshold Ramp down, EN = ’HI’, V5A > 4.5V, VFB = 100 mV, restart if 5-V dips below VPOR then rises > VUVLOH or EN is toggled with 5 V > VUVLOH 2.4 2.6 2.8
VPOR VDD fault latch Ramp down, EN = ‘HI’, VV5A > 4.5 V, can restart if 5-V supply rises to VUVLOH and no other faults present. 1.2 1.9 2.5
VINTFUVLOH VINTF UVLO OK Ramp up, EN = ’HI’, VV5A > 4.5 V, VVFB = 100 mV 1.4 1.5 1.6
VINTFUVLOL VINTF UVLO falling Ramp down, EN = ’HI’, VV5A > 4.5 V, VVFB = 100 mV 1.3 1.4 1.5
REFERENCES: DAC, VREF, VFB DISCHARGE
VVIDSTP VID step size Change VID0 HI to LO to HI 10 mV
VDAC1 VFB tolerance No load active, 1.36 V ≤ VVFB ≤ 1.52 V, IOUT = 0 A –9 9
VDAC2 VFB tolerance No load medium, 1.0 V ≤ VVFB ≤ 1.35 V, IOUT = 0 A –8 8
No load medium, 0.5 V ≤ VVFB ≤ 0.99 V, IOUT = 0 A -7 7
VVREF VREF output VREF output 4.5 V ≤ VV5A ≤ 5.5 V, IVREF = 0 A 1.66 1.700 1.74 V
VVREFSRC VREF output source 0 A ≤ IREF ≤ 500 µA, HP-2 –4 -3 mV
VVREFSNK VREF output sink –500 A ≤ IREF ≤ 0 A, HP-2 3 4
VVBOOT Internal VFB initial boot voltage Initial DAC boot voltage 0.99 1.00 1.01 V
RAMP SETTINGS
VRAMP Compensation ramp RRAMP = 30 kΩ 60 mV
RRAMP = 56 kΩ 120
RRAMP = 100 kΩ 160
RRAMP ≥ 150 kΩ 40
VOLTAGE SENSE: VFB AND GFB
RVFB VFB/GFB Input resistance Not in fault, disable or UVLO, VVFB = VDAC = 1.5 V,
VGFB = 0 V, measure from VFB to GFB		 1 MΩ
VDELGND GFB Differential GND to GFB ±100 mV
CURRENT MONITOR
VALADC IMON ADC output ∑∆CS = 0 mV, AIMON = 3.867 00h
∑∆CS = 1.5 mV, AIMON = 3.867 19h
∑∆CS = 7.5 mV, AIMON = 3.867 80h
∑∆CS = 15 mV, AIMON = 3.867 FFh
LRIMON IMON linear range Each phase, CSPx – CSNx 50 mV
CURRENT SENSE: OVER CURRENT PROTECTION, PHASE ADD AND DROP, AND PHASE BALANCE
VOCPP OCP voltage (valley current limit) ROCP-I = 20 kΩ 3.7 7.6 11.4 mV
ROCP-I = 24 kΩ 6.6 10.5 14.1
ROCP-I = 30 kΩ 10.6 14.5 18.0
ROCP-I = 39 kΩ 15.4 19.5 23.0
ROCP-I = 56 kΩ 21.3 25.4 29.0
ROCP-I = 75 kΩ 28.4 32.5 36.2
ROCP-I = 100 kΩ 36.3 40.5 44.0
ROCP-I = 150 kΩ 45.0 49.3 53.0
ICS CS pin input bias current CSPx and CSNx –500 0.2 500 nA
AV-EA Error amplifier total voltage gain(1) VFB to DROOP 80 dB
IEA_SR Error amplifier source current IDROOP, VVFB = VDAC + 50 mV, RCOMP = 1 kΩ 1 mA
IEA_SK Error amplifier sink current IDROOP, VVFB = VDAC – 50mV, RCOMP = 1 kΩ –1
ACSINT Internal current sense gain Gain from CSPx – CSNx to PWM comparator, RSKIP = Open 5.8 6.0 6.2 V/V
RSFTSTP Soft-stop transistor resistance Connected to CSN1 100 200 Ω
RVIN VIN resistance EN = HI 350 600 kΩ
EN = LOW or STBY 10 MΩ
PROTECTION: OVP, UVP, PGOOD AND THERMAL SHUTDOWN
VOVPH Fixed OVP voltage VCSN1 > VOVPH for 1 µs 1.60 1.70 1.80 V
VPGDH PGOOD high threshold Measured at the VFB pin w/r/t VID code, device latches OFF 190 245 mV
VPGDL PGOOD low threshold Measured at the VFB pin w/r/t VID code, device latches OFF -348 -280
PWM AND SKIP OUTPUTS: I/O VOLTAGE AND CURRENT
VP-S_L PWMx/SKIP - Low PWMILOAD = ± 1 mA, SKIPILOAD = ± 100 µA 0.15 0.3 V
VP-S_H PWMx/SKIP - High PWMILOAD = ± 1 mA, SKIPILOAD = ± 100 µA 4.2
LOGIC INTERFACE: VOLTAGE AND CURRENT
RVRTTL Pull-down resistance VSDA = 0.31 4 15 Ω
RVRPG VPGOOD= 0.31 36 50
IVRTTLK Logic leakage current VSCL= 1.8 V, VSDA = 1.8 V, VPGOOD = 3.3 V -2 0.2 2 µA
VIL Low-level Input voltage SCL, SDA; VVINTF = 1.8 V 0.6 V
VIH High-level Input voltage 1.2
IENH I/O leakage, EN Leakage current , VEN = 1.8 V 24 40 µA
(1) Specified by design. Not production tested.