SLVSB57C March   2012  – January 2016 TPS54060A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Bootstrap Voltage (BOOT)
      4. 7.3.4  Low Dropout Operation
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Voltage Reference
      7. 7.3.7  Adjusting the Output Voltage
      8. 7.3.8  Enable and Adjusting Undervoltage Lockout
      9. 7.3.9  Slow Start/Tracking Pin (SS/TR)
      10. 7.3.10 Overload Recovery Circuit
      11. 7.3.11 Sequencing
      12. 7.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      13. 7.3.13 Overcurrent Protection and Frequency Shift
      14. 7.3.14 Selecting the Switching Frequency
      15. 7.3.15 How to Interface to RT/CLK Pin
      16. 7.3.16 Power Good (PWRGD Pin)
      17. 7.3.17 Overvoltage Transient Protection
      18. 7.3.18 Thermal Shutdown
      19. 7.3.19 Small Signal Model for Loop Response
      20. 7.3.20 Simple Small Signal Model for Peak Current Mode Control
      21. 7.3.21 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Skip Eco-Mode
      2. 7.4.2 Normal Operation
      3. 7.4.3 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Output Inductor Selection (LO)
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Catch Diode
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Under Voltage Lock Out Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
        11. 8.2.2.11 Power Dissipation Estimate
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 66 for a PCB layout example. The GND pin should be tied directly to the power pad under the IC and the power pad.

The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching node, the catch diode and output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.

The estimated printed circuit board area for the components used in the design of Figure 51 is 0.55 in2. This area does not include test points or connectors.

10.2 Layout Example

TPS54060A layout_lvs795.gif Figure 66. PCB Layout Example