JAJS538D May 2011 – July 2016 TPS54062
PRODUCTION DATA.
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the GND pin. See Figure 50 for a PCB layout example. Since the PH connection is the switching node and output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The RT/CLK pin is sensitive to noise. so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts; however; this layout has been shown to produce good results and is meant as a guideline.
All sensitive analog traces and components such as VSENSE, RT/CLK and COMP should be placed away from high-voltage switching nodes such as PH, BOOT and inductor to avoid coupling. The topside resistor of the feedback voltage divider should be connected to the positive node of the VOUT capacitors or after the VOUT capacitors.