JAJS538D May   2011  – July 2016 TPS54062

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Error Amplifier
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Adjusting the Output Voltage
      6. 7.3.6  Enable and Adjusting Undervoltage Lockout
      7. 7.3.7  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      8. 7.3.8  Selecting the Switching Frequency
      9. 7.3.9  How to Interface to RT/CLK Pin
      10. 7.3.10 Overvoltage Transient Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Near Minimum Input Voltage
      2. 7.4.2 Operation With Enable Control
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Continuous Conduction Mode (CCM) Switching Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Selecting the Switching Frequency
          2. 8.2.1.2.2 Output Inductor Selection (LO)
          3. 8.2.1.2.3 Output Capacitor
          4. 8.2.1.2.4 Input capacitor
          5. 8.2.1.2.5 Bootstrap Capacitor Selection
          6. 8.2.1.2.6 Under Voltage Lock Out Set Point
          7. 8.2.1.2.7 Output Voltage and Feedback Resistors Selection
          8. 8.2.1.2.8 Closing the Loop
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DCM Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Closing the Feedback Loop
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

MSOP PACKAGE
8 PINS
TOP VIEW
TPS54062 po_lvsav1.gif
VSON PACKAGE
8 PINS
BOTTOM VIEW
TPS54062 po2_lvsav1.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NUMBER
BOOT 1 O A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
VIN 2 I Input supply voltage, 4.7 V to 60 V.
EN 3 I Enable pin, internal pull-up current source. Pull below 1.14 V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors, see the Enable and Adjusting Undervoltage Lockout section.
RT/CLK 4 I Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor frequency programming.
VSENSE 5 I Inverting input of the transconductance (gm) error amplifier.
COMP 6 O Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin.
GND 7 – Ground
PH 8 O The source of the internal high-side power MOSFET and drain of the internal low side MOSFET
Thermal Pad 9 – GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. VSON-8 package only.