JAJSOW4A September   2009  – January 2024 TPS5410-Q1

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5. 4静電気放電に関する注意事項
  6. 5Ordering Information
  7. 6Pin Assignments
    1. 6.1 Terminal Functions
  8. 7Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information 
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8Application Information
    1. 8.1 Functional Block Diagram
    2. 8.2 Detailed Description
      1. 8.2.1  Oscillator Frequency
      2. 8.2.2  Voltage Reference
      3. 8.2.3  Enable (ENA) and Internal Slow Start
      4. 8.2.4  Undervoltage Lockout (UVLO)
      5. 8.2.5  Boost Capacitor (BOOT)
      6. 8.2.6  Output Feedback (VSENSE)
      7. 8.2.7  Internal Compensation
      8. 8.2.8  Voltage Feed Forward
      9. 8.2.9  Pulse-Width-Modulation (PWM) Control
      10. 8.2.10 Overcurrent Liming
      11. 8.2.11 Overvoltage Protection
      12. 8.2.12 Thermal Shutdown
      13. 8.2.13 PCB Layout
      14. 8.2.14 Application Circuits
      15. 8.2.15 Design Procedure
        1. 8.2.15.1 Design Parameters
        2. 8.2.15.2 Switching Frequency
        3. 8.2.15.3 Input Capacitors
        4. 8.2.15.4 Output Filter Components
          1. 8.2.15.4.1 Inductor Selection
          2. 8.2.15.4.2 Capacitor Selection
          3.        40
          4.        41
        5. 8.2.15.5 Output Voltage Setpoint
        6. 8.2.15.6 Boot Capacitor
        7. 8.2.15.7 Catch Diode
        8. 8.2.15.8 Additional Circuits
      16. 8.2.16 Output Filter Capacitor Selection
      17. 8.2.17 External Compensation Network
    3. 8.3 Advanced Information
      1. 8.3.1 Output Voltage Limitations
      2. 8.3.2 Internal Compensation Network
      3. 8.3.3 Thermal Calculations
    4. 8.4 Performance Graphs
    5. 8.5 Performance Graphs
  10. 9Revision History

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.6 Output Feedback (VSENSE)

The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage reference 1.221 V.