JAJS298D DECEMBER   2003  – June 2019 TPS54110

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
  4. 4 改訂履歴
  5. 5 Device Information
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Thermal Information
    4. 7.4 Electrical Characteristics
    5. 7.5 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VBIAS Regulator (VBIAS)
      2. 8.3.2 Voltage Reference
      3. 8.3.3 Oscillator and PWM Ramp
      4. 8.3.4 Error Amplifier
      5. 8.3.5 PWM Control
      6. 8.3.6 Dead-Time Control and MOSFET Drivers
      7. 8.3.7 Overcurrent Protection
      8. 8.3.8 Thermal Shutdown
      9. 8.3.9 Power Good (PWRDG)
    4. 8.4 Undervoltage Lockout (UVLO)
    5. 8.5 Slow-Start/Enable (SS/ENA)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical TPS54110 Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Switching Frequency
          2. 9.2.1.2.2 Input Capacitors
          3. 9.2.1.2.3 Output Filter Components
            1. 9.2.1.2.3.1 Inductor Selection
            2. 9.2.1.2.3.2 Capacitor Selection
          4. 9.2.1.2.4 Compensation Components
          5. 9.2.1.2.5 Bias and Bootstrap Capacitors
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Very-Small Form-Factor Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Two-Output Sequenced-Startup Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Layout Considerations For Thermal Performance
    4. 10.4 Grounding and Powerpad Layout
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PWP|20
サーマルパッド・メカニカル・データ
発注情報

7.4 Electrical Characteristics

TJ = –40°C to +125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE, VIN
VIN input voltage range 3 6 V
Quiescent current fs = 350 kHz, SYNC ≤ 0.8 V, RT open 4.5 8.5 mA
fs = 550 kHz, Phase pin open,
SYNC ≥ 2.5 V, RT open,		 5.8 9.6
Shutdown, SS/ENA = 0 V 1 1.4
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO 2.95 3 V
Stop threshold voltage, UVLO 2.70 2.80
Hysteresis voltage, UVLO 0.12 V
Rising and falling edge deglitch, UVLO(1) 2.5 µs
BIAS VOLTAGE
VO Output voltage, VBIAS I(VBIAS) = 0 2.70 2.80 2.90 V
Output current, VBIAS(2) 100 µA
CUMULATIVE REFERENCE
Vref Accuracy 0.882 0.891 0.900 V
REGULATION
Line regulation(1)(3) IL = 0.75 A, fs = 350 kHz, TJ = 85°C 0.05 %/V
IL = 0.75 A, fs = 550 kHz, TJ = 85°C 0.05
Load regulation(1)(3) IL = 0 A to 1.5 A, fs = 350 kHz, TJ = 85°C 0.01 %/A
IL = 0 A to 1.5 A fs = 550 kHz, TJ = 85°C 0.01
OSCILLATOR
Internally set free-running frequency range SYNC ≤ 0.8 V, RT open 280 350 420 kHz
SYNC ≥ 2.5 V, RT open 440 550 660
Externally set free-running frequency range RT = 180 kΩ (1% resistor to AGND)(1) 252 280 308 kHz
RT = 100 kΩ (1% resistor to AGND) 460 500 540
RT = 68 kΩ (1% resistor to AGND)(1) 663 700 762
High-level threshold voltage, SYNC 2.5 V
Low-level threshold voltage, SYNC 0.8 V
Pulse duration, SYNC(1) 50 ns
Frequency range, SYNC(1) 330 700 kHz
Ramp valley(1) 0.75 V
Ramp amplitude (peak-to-peak)(1) 1 V
Minimum controllable on time(1) 200 ns
Maximum duty cycle 90 %
ERROR AMPLIFIER
Error-amplifier open loop voltage gain 1 kΩ COMP to AGND(1) 90 110 dB
Error-amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND(1) 3 5 MHz
Error-amplifier common-mode input voltage range Powered by internal LDO(1) 0 VBIAS V
IIB Input bias current, VSENSE VSENSE = Vref 60 250 nA
VO Output voltage slew rate (symmetric), COMP(1) 1.2 V/µs
PWM COMPARATOR
PWM comparator propagation delay time, PWM comparator input to PH pin (excluding dead time) 10 mV overdrive(1) 70 85 ns
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA 0.82 1.20 1.40 V
Enable hysteresis voltage, SS/ENA(1) 0.03 V
Falling-edge deglitch, SS/ENA(1) 2.5 µs
Internal slow-start time 2.6 3.35 4.1 ms
Charge current, SS/ENA SS/ENA = 0 V 3 5 8 µA
Discharge current, SS/ENA SS/ENA = 1.3 V, VI = 1.5 V 1.5 2.3 4 mA
POWER GOOD
Power-good threshold voltage VSENSE falling 93 %Vref
Power-good hysteresis voltage(1) 3 %Vref
Power-good falling-edge deglitch(1) 35 µs
Output saturation voltage, PWRGD I(sink) = 2.5 mA 0.18 0.30 V
Leakage current, PWRGD VI = 5.5 V 1 µA
CURRENT LIMIT
Current limit trip point VI = 3 V, output shorted(1) 3.0 A
VI = 6 V, output shorted(1) 3.5
Current-limit leading edge blanking time 100 ns
Current-limit total response time 200 ns
THERMAL SHUTDOWN
Thermal-shutdown trip point(1) 135 150 165 °C
Thermal-shutdown hysteresis(1) 10 °C
OUTPUT POWER MOSFETS
rDS(on) Power MOSFET switches(5) IO = 1.5 A, VI = 6 V(4) 240 480 mΩ
IO = 1.5 A, VI = 3 V(4) 345 690
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 9.
(4) Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design
(5) Includes package and bondwire resistance