JAJS298D DECEMBER   2003  – June 2019 TPS54110

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
  4. 4 改訂履歴
  5. 5 Device Information
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Thermal Information
    4. 7.4 Electrical Characteristics
    5. 7.5 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VBIAS Regulator (VBIAS)
      2. 8.3.2 Voltage Reference
      3. 8.3.3 Oscillator and PWM Ramp
      4. 8.3.4 Error Amplifier
      5. 8.3.5 PWM Control
      6. 8.3.6 Dead-Time Control and MOSFET Drivers
      7. 8.3.7 Overcurrent Protection
      8. 8.3.8 Thermal Shutdown
      9. 8.3.9 Power Good (PWRDG)
    4. 8.4 Undervoltage Lockout (UVLO)
    5. 8.5 Slow-Start/Enable (SS/ENA)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical TPS54110 Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Switching Frequency
          2. 9.2.1.2.2 Input Capacitors
          3. 9.2.1.2.3 Output Filter Components
            1. 9.2.1.2.3.1 Inductor Selection
            2. 9.2.1.2.3.2 Capacitor Selection
          4. 9.2.1.2.4 Compensation Components
          5. 9.2.1.2.5 Bias and Bootstrap Capacitors
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Very-Small Form-Factor Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Two-Output Sequenced-Startup Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curve
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Layout Considerations For Thermal Performance
    4. 10.4 Grounding and Powerpad Layout
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PWP|20
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PWP Package
20-Pin HTSSOP With PowerPAD
Top View
TPS54110 po_lvs500.gif

Pin Functions

PIN DESCRIPTION
NAME NO.
AGND 1 Analog ground—internally connected to the sensitive analog-ground circuitry. Connect to PGND and PowerPAD.
BOOT 5 Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver.
COMP 3 Error amplifier output. Connect compensation network from COMP to VSENSE.
PGND 11–13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. Connect to AGND and PowerPAD.
PH 6–10 Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
PWRGD 4 Power-good open drain output. High when VSENSE ≥ 93% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or internal shutdown signal active.
RT 20 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA 18 Slow-start/enable input/output. Dual-function pin that provides logic input to enable/disable device operation and capacitor input to externally set the start-up time.
SYNC 19 Synchronization input. Dual-function pin that provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin.
VBIAS 17 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low ESR 0.1-µF to 1-µF ceramic capacitor.
VIN 14–16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
VSENSE 2 Error amplifier inverting input.