JAJS381E September   2009  – September 2018 TPS54218

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation and Output Current
      3. 8.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 8.3.4  Error Amplifier
      5. 8.3.5  Voltage Reference
      6. 8.3.6  Adjusting the Output Voltage
      7. 8.3.7  Enable and Adjusting Undervoltage Lockout
      8. 8.3.8  Soft-Start Pin
      9. 8.3.9  Sequencing
      10. 8.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 8.3.11 Overcurrent Protection
      12. 8.3.12 Frequency Shift
      13. 8.3.13 Reverse Overcurrent Protection
      14. 8.3.14 Synchronize Using the RT/CLK Pin
      15. 8.3.15 Power Good (PWRGD Pin)
      16. 8.3.16 Overvoltage Transient Protection
      17. 8.3.17 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Small Signal Model for Loop Response
      2. 8.4.2 Simple Small Signal Model for Peak Current Mode Control
      3. 8.4.3 Small Signal Model for Frequency Compensation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Step One: Select the Switching Frequency
        2. 9.2.2.2  Step Two: Select the Output Inductor
        3. 9.2.2.3  Step Three: Choose the Output Capacitor
        4. 9.2.2.4  Step Four: Select the Input Capacitor
        5. 9.2.2.5  Step Five: Minimum Load DC COMP Voltage
        6. 9.2.2.6  Step Six: Choose the Soft-Start Capacitor
        7. 9.2.2.7  Step Seven: Select the Bootstrap Capacitor
        8. 9.2.2.8  Step Eight: Undervoltage Lockout Threshold
        9. 9.2.2.9  Step Nine: Select Output Voltage and Feedback Resistors
          1. 9.2.2.9.1 Output Voltage Limitations
        10. 9.2.2.10 Step 10: Select Loop Compensation Components
        11. 9.2.2.11 Power Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 WEBENCH®ツールによるカスタム設計
      2. 12.1.2 開発サポート
    2. 12.2 商標
    3. 12.3 静電気放電に関する注意事項
    4. 12.4 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.3 Application Curves

TPS54218 eff_io_lvs974.gif
Figure 38. Efficiency vs Load Current
TPS54218 trns_res_lvs974.gif
1-A Load Step
Figure 40. Transient Response
TPS54218 pwr_up_lvs974.gif
Figure 42. Power Up, VOUT, VIN
TPS54218 pwr_up2_lvs974.gif
Figure 44. Power Up, VOUT, EN
TPS54218 stop_start_en_slvs974.gif
1.
Figure 46. SS Discharge During EN Disable / Enable
TPS54218 oripp2_lvs974.gif
IOUT = 2 A
Figure 48. Output Ripple
TPS54218 iripp2_lvs974.gif
IOUT = 2A
Figure 50. Input Ripple
TPS54218 vo_io_lvs974.gif
Figure 52. Load Regulation vs Load Current
TPS54218 vo_vi_lvs974.gif
Figure 54. Regulation vs Input Voltage
TPS54218 eff_io2_lvs974.gif
Figure 39. Efficiency vs Load Current
TPS54218 trns_res2_lvs974.gif
2-A Load Step
Figure 41. Transient Response
TPS54218 pwr_dwn_lvs974.gif
Figure 43. Power Down, VOUT, VIN
TPS54218 stop_en_slvs974.gif
Figure 45. Power Down, VOUT, EN
TPS54218 oripp_lvs974.gif
IOUT = 0 A
Figure 47. Output Ripple
TPS54218 iripp_lvs974.gif
IOUT = 0 A
Figure 49. Input Ripple
TPS54218 loop_resp_lvs974.gif
VIN = 3.3. V IOUT = 2 A
Figure 51. Closed Loop Response
TPS54218 vo2_io_lvs974.gif
Figure 53. Load Regulation vs Load Current