JAJSCU9 December   2016 TPS54262-EP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Unregulated Input Voltage
      2. 7.3.2  Regulated Output Voltage
      3. 7.3.3  Regulation and Feedback Voltage
      4. 7.3.4  Enable and Shutdown
      5. 7.3.5  Soft Start
      6. 7.3.6  Oscillator Frequency
        1. 7.3.6.1 Selecting the Switching Frequency
        2. 7.3.6.2 Synchronization With External Clock
      7. 7.3.7  Slew Rate Control
      8. 7.3.8  Reset
      9. 7.3.9  Reset Delay
      10. 7.3.10 Reset Threshold and Undervoltage Threshold
      11. 7.3.11 Overvoltage Supervisor
      12. 7.3.12 Noise Filter on RST_TH and OV_TH Terminals
      13. 7.3.13 Boot Capacitor
      14. 7.3.14 Short Circuit Protection
      15. 7.3.15 Overcurrent Protection
      16. 7.3.16 Internal Undervoltage Lockout (UVLO)
      17. 7.3.17 Thermal Shutdown (TSD)
      18. 7.3.18 Loop Control Frequency Compensation - Type 3
        1. 7.3.18.1 Bode Plot of Converter Gain
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode Continuous Conduction Mode (CCM)
      2. 7.4.2 Active Mode Discontinuous Conduction Mode (DCM)
      3. 7.4.3 Pulse Skip Mode (PSM)
      4. 7.4.4 Low-Power Mode (LPM)
      5. 7.4.5 Hysteretic Mode
      6. 7.4.6 Output Tolerances in Different Modes of Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection
          1. 8.2.2.1.1  Input Capacitors (C1, C11)
          2. 8.2.2.1.2  Output Capacitor (C4, C12)
          3. 8.2.2.1.3  Soft-Start Capacitor (C6)
          4. 8.2.2.1.4  Bootstrap Capacitor (C3)
          5. 8.2.2.1.5  Power-On Reset Delay (PORdly) Capacitor (C2)
          6. 8.2.2.1.6  Output Inductor (L1)
          7. 8.2.2.1.7  Flyback Schottky Diode (D2)
          8. 8.2.2.1.8  Resistor to Set Slew Rate (R7)
          9. 8.2.2.1.9  Resistor to Select Switching Frequency (R8)
          10. 8.2.2.1.10 Resistors to Select Output Voltage (R4, R5)
          11. 8.2.2.1.11 Resistors to Set Undervoltage, Overvoltage, and Reset Thresholds (R1, R2, R3)
            1. 8.2.2.1.11.1 Overvoltage Resistor Selection
            2. 8.2.2.1.11.2 Reset Threshold Resistor Selection
            3. 8.2.2.1.11.3 Undervoltage Threshold for Low-Power Mode and Load Transient Operation
          12. 8.2.2.1.12 Low-Power Mode (LPM) Threshold
          13. 8.2.2.1.13 Enable Pin Pull-Up Resistor (R11) and Voltage Divider Resistor (R10)
          14. 8.2.2.1.14 Pull-Up Resistor (R12) at RST Pin
          15. 8.2.2.1.15 Type 3 Compensation Components (R5, R6, R9, C5, C7, C8)
            1. 8.2.2.1.15.1 Resistors
            2. 8.2.2.1.15.2 Capacitors
          16. 8.2.2.1.16 Noise Filter on RST_TH and OV_TH Terminals (C9, C10)
        2. 8.2.2.2 Design Example 1
          1. 8.2.2.2.1  Calculate the Switching Frequency (fsw)
          2. 8.2.2.2.2  Calculate the Ripple Current (IRipple)
          3. 8.2.2.2.3  Calculate the Inductor Value (L1)
          4. 8.2.2.2.4  Calculate the Output Capacitor and ESR (C4)
            1. 8.2.2.2.4.1 Calculate Capacitance
            2. 8.2.2.2.4.2 Calculate ESR
          5. 8.2.2.2.5  Calculate the Feedback Resistors (R4, R5)
          6. 8.2.2.2.6  Calculate Type 3 Compensation Components
            1. 8.2.2.2.6.1 Resistances (R6, R9)
            2. 8.2.2.2.6.2 Capacitors (C5, C8, C7)
          7. 8.2.2.2.7  Calculate Soft-Start Capacitor (C6)
          8. 8.2.2.2.8  Calculate Bootstrap Capacitor (C3)
          9. 8.2.2.2.9  Calculate Power-On Reset Delay Capacitor (C2)
          10. 8.2.2.2.10 Calculate Input Capacitor (C1, C11)
          11. 8.2.2.2.11 Calculate Resistors to Control Slew Rate (R7)
          12. 8.2.2.2.12 Resistors to Select Undervoltage, Overvoltage and Reset Threshold Values (R1, R2, R3)
          13. 8.2.2.2.13 Diode D1 and D2 Selection
          14. 8.2.2.2.14 Noise Filter on RST_TH and OV_TH Terminals (C9 and C10)
          15. 8.2.2.2.15 Power Budget and Temperature Estimation
        3. 8.2.2.3 Design Example 2
          1. 8.2.2.3.1  Calculate the Switching Frequency (fsw)
          2. 8.2.2.3.2  Calculate the Ripple Current (IRipple)
          3. 8.2.2.3.3  Calculate the Inductor Value (L1)
          4. 8.2.2.3.4  Calculate the Output Capacitor and ESR (C4, C12)
            1. 8.2.2.3.4.1 Calculate Capacitance
            2. 8.2.2.3.4.2 Calculate ESR
          5. 8.2.2.3.5  Calculate the Feedback Resistors (R4, R5)
          6. 8.2.2.3.6  Calculate Type 3 Compensation Components
            1. 8.2.2.3.6.1 Resistances (R6, R9)
            2. 8.2.2.3.6.2 Capacitors (C5, C8, C7)
          7. 8.2.2.3.7  Calculate Soft-Start Capacitor (C6)
          8. 8.2.2.3.8  Calculate Bootstrap Capacitor (C3)
          9. 8.2.2.3.9  Calculate Power-On Reset Delay Capacitor (C2)
          10. 8.2.2.3.10 Calculate Input Capacitor (C1, C11)
          11. 8.2.2.3.11 Calculate Resistors to Control Slew Rate (R7)
          12. 8.2.2.3.12 Resistors to Select Undervoltage, Overvoltage and Reset Threshold Values (R1, R2, R3)
          13. 8.2.2.3.13 Diode D1 and D2 Selection
          14. 8.2.2.3.14 Noise Filter on RST_TH and OV_TH Terminals (C9 and C10)
          15. 8.2.2.3.15 Power Budget and Temperature Estimation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation and Temperature Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

A proper layout is critical for the operation of a switched-mode power supply, even more at high switching frequencies. Therefore, the PCB layout of the TPS54262-EP device demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (line and load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity. See Figure 29 for recommended layout example for TPS54262-EP device.

  • It is critical to provide a low-inductance, low-impedance ground path and hence use wide and short traces for the main current paths.
  • The input capacitor, catch diode, output capacitor, and inductor should be placed as close as possible to the IC pins and use thick traces (low impedance path) to connect them.
  • Route the feedback trace so that there is minimum interaction with any noise sources associated with the switching components. Recommended practice is to place the inductor away from the feedback trace to prevent EMI noise.
  • Place compensation network components away from switching components and route their connections away from noisy area.
  • In a two-sided PCB, TI recommends having ground planes on both sides of the PCB to help reduce noise and ground-loop errors. Connect the ground connection for the input and output capacitors and IC ground to this ground plane.
  • In a multilayer PCB, the ground plane separates the power plane (where high switching currents and components are placed) from the signal plane (where the feedback trace and components are) for improved performance.
  • Also, arrange the components such that the switching-current loops curl in the same direction. Place the high-current components such that during conduction the current path is in the same direction. Doing so prevents magnetic field reversal caused by the traces between the two half cycles, helping to reduce radiated EMI.
  • Add multiple thermal via's on the device thermal pad for better thermal performance.

10.2 Layout Example

TPS54262-EP pcb_layout_lvs845.gif Figure 29. PCB Layout Example

10.3 Power Dissipation and Temperature Considerations

The power dissipation losses are applicable for continuous conduction mode operation (CCM). The total power dissipated by the device is the sum of the following power losses.

Conduction losses, PCON

Equation 43. TPS54262-EP eq_pcon_lvs996.gif

Switching losses, PSW

Equation 44. TPS54262-EP eq_psw_lvs996.gif

Gate drive losses, PGate

Equation 45. PGate = Vdrive × Qg × fsw

Power supply losses, PIC

Equation 46. PIC = VIN × Iq-Normal

Therefore, the total power dissipated by the device is given by Equation 47.

Equation 47. PTotal = PCON + PSW + PGate + PIC

where

  • VIN = unregulated input voltage
  • ILoad = output load current
  • tr = FET switching rise time (tr= 40 ns (maximum))
  • tf = FET switching fall time
  • fsw = switching frequency
  • Vdrive = FET gate drive voltage (Vdrive = 6 V (typical), Vdrive = 8 V (maximum))
  • Qg = 1×10–9 C
  • Iq-Normal = quiescent current in normal mode (Active Mode CCM)

For device under operation at a given ambient temperature (TA), the junction temperature (TJ) can be calculated using Equation 48.

Equation 48. TJ = TA + (Rth × PTotal)

Therefore, the rise in junction temperature due to power dissipation is shown in Equation 49.

Equation 49. ΔT = TJ – TA = (Rth × PTotal)

For a given maximum junction temperature (TJ-Max), the maximum ambient temperature (TA-Max) in which the device can operate is calculated using Equation 50.

Equation 50. TA-Max = TJ-Max – (Rth × PTotal)

where

  • TJ = junction temperature in °C
  • TA = ambient temperature in °C
  • Rth = thermal resistance of package in W/°C
  • TJ-Max = maximum junction temperature in °C
  • TA-Max = maximum ambient temperature in °C

There are several other factors that also affect the overall efficiency and power losses. Examples of such factors are AC and DC losses in the inductor, voltage drop across the copper traces on PCB, power losses in the flyback catch diode and so forth. The previous discussion does not include such factors.

TPS54262-EP pwr_diss_slvsdp3.gif Figure 30. Power Dissipation vs Ambient Temperature

NOTE

The output current rating for the regulator may must be derated for ambient temperatures above 85°C. The derated value will depend on calculated worst-case power dissipation and the thermal management implementation in the application.