JAJSCU9 データシート

JAJSCU9 December 2016 TPS54262-EP

PRODUCTION DATA.

パッケージ・オプション

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
Input voltage	EN		–0.3	60	V
	VIN		–0.3	60
	VReg		–0.3	20
	LPM		–0.3	5.5
	OV_TH		–0.3	5.5
	RST_TH		–0.3	5.5
	SYNC		–0.3	5.5
	VSENSE		–0.3	5.5
Output voltage	BOOT		–0.3	65	V
	PH	DC voltage	–0.3	60
		DC voltage, T_J = –55°C	–0.85
		DC voltage, T_J = 125°C	–0.5
		30-ns transient pulse	–2
		200-ns transient pulse	–1
	RT		–0.3	5.5
	RST		–0.3	5.5
	Cdly		–0.3	8
	SS		–0.3	8
	COMP		–0.3	7
Operating virtual junction temperature, T_J			–55	150	°C
Storage temperature, T_stg			–55	165	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾		±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_I	Unregulated buck supply input voltage (VIN, EN)		3.6	48	V
V_Reg	Regulated output voltage	In continuous conduction mode (CCM)	0.9	18	V
V_Reg	Regulated output voltage	Power up in low-power mode (LPM) or discontinuous conduction mode (DCM)	0.9	5.5	V
	Bootstrap capacitor (BOOT)		3.6	56	V
	Switched outputs (PH)		3.6	48	V
	Logic levels (RST, VSENSE, OV_TH, RST_TH, Rslew, SYNC, RT)		0	5.25	V
	Logic levels (SS, Cdly, COMP)		0	6.5	V
T_A	Operating ambient temperature		–55	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS54262-EP	UNIT
		PWP (HTSSOP)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	37.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	20.8	°C/W
R_θJB	Junction-to-board thermal resistance	8.7	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	8.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 DC Electrical Characteristics

VIN = 7 V to 48 V, EN = VIN, T_J = –55°C to 150°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		TEST⁽¹⁾	MIN	TYP	MAX	UNIT
INPUT POWER SUPPLY
VIN	Supply voltage on VIN	Normal mode: after initial start-up		Info	3.6		48	V
		Low-power mode	Falling threshold (LPM disabled)			8
			Rising threshold (LPM activated)			8.5
			High voltage threshold (LPM disabled)		29	31	34
I_q-Normal	Quiescent current, normal mode	Open loop test – maximum duty cycle VIN = 7 V to 48 V		PT		5	10	mA
I_q-LPM	Quiescent current, low-power mode	I_Load < 1 mA, VIN = 12 V	T_A = 25°C	PT		50	70	µA
		I_Load < 1 mA, VIN = 12 V	–55 < T_J < 150°C				75
		I_Load < 1 mA, VIN = 24 V	T_A= 25°C				75
		I_Load < 1 mA, VIN = 24 V	–55 < T_J < 150°C				75
I_SD	Shutdown current	EN = 0 V, device is off	T_A = 25°C, VIN = 12 V	PT		1	4	µA
TRANSITION TIMES (LOW POWER – NORMAL MODES)
t_d1	Transition delay, normal mode to low-power mode	VIN = 12 V, V_Reg = 5 V, I_Load = 1 A to 1 mA		CT		100		µs
t_d2	Transition delay, low-power mode to normal mode	VIN = 12 V, V_Reg = 5 V I_Load = 1 mA to 1 A		CT		5		µs
SWITCH MODE SUPPLY; V_Reg
V_Reg	Regulator output	VSENSE = 0.8 V_ref		Info	0.9		18	V
VSENSE	Feedback voltage	V_Reg = 0.9 V to 18 V (open loop)		CT	0.788	0.8	0.812	V
R_DS(ON)	Internal switch resistance	Measured across VIN and PH, I_Load = 500 mA		PT			500	mΩ
I_CL	Switch current limit, cycle by cycle	VIN = 12 V		Info	2.5	3.2	4.1	A
t_ON-Min	Duty cycle pulse width	Bench CHAR only		Info	50	100	150	ns
t_OFF-Min		Bench CHAR only		Info	100	200	250	ns
f_sw	Switching frequency	Set using external resistor on RT pin		PT	0.2		2.2	MHz
f_sw	Internal oscillator frequency tolerance			PT	–10%		10%
I_Sink	Start-up condition	OV_TH = 0 V, V_Reg = 10 V		Info			1	mA
I_Limit	Prevent overshoot	0 V < OV_TH < 0.8 V, V_Reg = 10 V		Info			80	mA
ENABLE (EN)
V_IL	Low input threshold voltage			PT			0.7	V
V_IH	High input threshold voltage			PT	1.7			V
I_lkg	Leakage current into EN terminal	EN = 60 V		PT		100	135	µA
I_lkg	Leakage current into EN terminal	EN = 12 V		PT		8	15	µA
RESET DELAY (Cdly)
I_O	External capacitor charge current	EN = high		PT	1.4	2	3	µA
V_Threshold	Switching threshold voltage	Output voltage in regulation		PT		2		V
LOW-POWER MODE (LPM)
V_IL	Low input threshold voltage	VIN = 12 V		PT			0.7	V
V_IH	High input threshold voltage	VIN = 12 V		PT	1.7			V
I_lkg	Leakage current into LPM terminal	LPM = 5 V		PT		65	95	µA
RESET OUTPUT (RST)
t_rdly	POR delay timer	Based on Cdly capacitor		PT	3.2		7	ms/nF
VReg_RST	Reset threshold voltage for V_Reg	Check RST output		PT	0.768		0.832	V
t_nRSTdly	Filter time	Delay before RST is asserted low		PT	10	20	35	µs
SOFT START (SS)
I_SS	Soft-start source current			PT	40	50	60	µA
SYNCHRONIZATION (SYNC)
V_IL	Low input threshold voltage			PT			0.7	V
V_IH	High input threshold voltage			PT	1.7			V
I_lkg	Leakage current	SYNC = 5 V		PT		65	95	µA
SYNC (f_ext)	External input clock frequency	VIN = 12 V, V_Reg = 5 V, 180 kHz < f_sw < f_ext < 2 × f_sw < 2.2 MHz		CT	180		2200	kHz
SYNC_trans	External clock to internal clock	No external clock, VIN = 12 V, V_Reg = 5 V		Info		32		µs
SYNC_trans	Internal clock to external clock	External clock = 1 MHz, VIN = 12 V, V_Reg = 5 V		Info		2.5		µs
SYNC_CLK	Minimum duty cycle			CT	30%
SYNC_CLK	Maximum duty cycle			CT			70%
Rslew
I_Rslew	Rslew = 50 kΩ			CT		20		µA
I_Rslew	Rslew = 10 kΩ			CT		100		µA
OVERVOLTAGE SUPERVISORS (OV_TH)
VReg_OV	Threshold voltage for V_Reg during overvoltage	Internal switch is turned off		PT	0.768		0.832	V
VReg_OV	V_Reg = 5 V	Internal pulldown on V_Reg, OV_TH = 1 V		PT		70⁽²⁾		mA
THERMAL SHUTDOWN
T_SD	Thermal shutdown junction temperature			CT		175		°C
T_HYS	Hysteresis			CT		30		°C

(1) PT: Production tested
CT: Characterization tested only, not production tested
Info: User information only, not production tested

(2) This is the current flowing into the VReg pin when voltage at OV_TH pin is 1 V.

6.6 Typical Characteristics

VIN = 14 V	V_Reg = 5 V	f_sw = 500 kHz
L = 22 µH	C = 100 µF	T_A = 25°C

Figure 1. Efficiency vs Load Current for Different Rslew Resistors

	EN not connected to VIN

Figure 3. LPM, Quiescent Current Variation With Temperature

Figure 5. Output Voltage vs Input Voltage for Different Load Currents ⁽¹⁾

V_Reg = 5 V	f_sw = 500 kHz	L = 22 µH
C = 100 µF	Rslew = 30 kΩ	T_A = 25°C

Figure 2. Efficiency vs Load Current for Different Vin

	EN not connected to VIN

Figure 4. Shutdown Current Variation With Temperature

V_Reg = 5 V	T_A = 25°C

Figure 6. Input Voltage vs Load Current During Power Up and Power Down ^{shows the dropout operation during low input conditions.}

1. Figure 5shows the dropout operation during low input conditions.
Figure 6 shows the following plots:
(a) Power Up (Start Up): Input voltage required to achieve the 5-V regulation during power up over the range of load currents
(b) Power Down (Tracking): Input voltage at which the output voltage drops approximately by 0.7 V from the programmed 5-V regulated voltage

VIN = 12 V	EN = high

Figure 7. Internal Reference Voltage

VIN = 12 V	EN = high

Figure 9. Current Consumption With Temperature

VIN = 12 V	EN = high

Figure 8. Voltage Drop ON Rslew for Current Reference (Slew Rate / Rslew)