JAJSK12C September 2020 – December 2021 TPS542A50
PRODUCTION DATA
An output overvoltage (OV) fault is triggered if the output voltage, sensed by RSP/RSN, is greater than the OVP trip level. When this condition is detected, the converter terminates the switching cycle and turns on the low-side FET to discharge the output voltage. The low-side FET remains on until the low-side FET current reaches the negative overcurrent limit. When the negative overcurrent limit is reached, the low set FET turns off for 2000 ns. After the 2000 ns delay, the low-side FET turns back on until the negative overcurrent limit is reached. This process repeats until the output voltage is discharged below the undervoltage fault threshold (typically 80% set VOUT). The converter then enters hiccup for seven cycles of soft-start CLK frequency due to the output voltage being below the UV threshold.
An output undervoltage fault is triggered if the output voltage, sensed by RSP/RSN, is less than UVP threshold. When this condition is detected, power conversion is disabled, and the converter enters hiccup for seven cycles of soft-start CLK frequency.