JAJS289F December   2001  – April 2019 TPS54310

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Dissipation Ratings
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Lockout (UVLO)
      2. 8.3.2  Slow Start and Enable (SS/ENA)
      3. 8.3.3  VBIAS Regulator (VBIAS)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Oscillator and PWM Ramp
      6. 8.3.6  Error Amplifier
      7. 8.3.7  PWM Control
      8. 8.3.8  Dead-Time Control and MOSFET Drivers
      9. 8.3.9  Overcurrent Protection
      10. 8.3.10 Thermal Shutdown
      11. 8.3.11 Powergood (PWRGD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conduction Mode
      2. 8.4.2 Switching Frequency Configuration
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Voltage
        2. 9.2.2.2 Feedback Circuit
        3. 9.2.2.3 Setting the Output Voltage
        4. 9.2.2.4 Operating Frequency
        5. 9.2.2.5 Output Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連する DC/DC 製品
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 Typical Characteristics

TPS54310 tc_ds_tj_lvs412.gif
Figure 1. Drain-Source On-State Resistance vs Junction Temperature
TPS54310 _tc_of_tj_lvs412.gif
Figure 3. Internally Set Oscillator Frequency vs Junction Temperature
TPS54310 tc_vref_tj_lvs412.gif
Figure 5. Voltage Reference vs Junction Temperature
TPS54310 tc_err_amp_lvs412.gif
Figure 7. Error Amplifier Open Loop Response
TPS54310 tc_pl_il_lvs412.gif
Figure 9. Device Power Losses vs Load Current
TPS54310 tc_ds2_tj_lvs412.gif
Figure 2. Drain-Source On-State Resistance vs Junction Temperature
TPS54310 tc_of2_tj_lvs412.gif
Figure 4. Externally Set Oscillator Frequency vs Junction Temperature
TPS54310 tc_vo_vi_lvs412.gif
Figure 6. Output Voltage Regulation vs Input Voltage
TPS54310 tc_ss_tj_lvs412.gif
Figure 8. Internal Slow-Start Time vs Junction Temperature