JAJS289F December   2001  – April 2019 TPS54310

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Dissipation Ratings
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Lockout (UVLO)
      2. 8.3.2  Slow Start and Enable (SS/ENA)
      3. 8.3.3  VBIAS Regulator (VBIAS)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Oscillator and PWM Ramp
      6. 8.3.6  Error Amplifier
      7. 8.3.7  PWM Control
      8. 8.3.8  Dead-Time Control and MOSFET Drivers
      9. 8.3.9  Overcurrent Protection
      10. 8.3.10 Thermal Shutdown
      11. 8.3.11 Powergood (PWRGD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conduction Mode
      2. 8.4.2 Switching Frequency Configuration
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Voltage
        2. 9.2.2.2 Feedback Circuit
        3. 9.2.2.3 Setting the Output Voltage
        4. 9.2.2.4 Operating Frequency
        5. 9.2.2.5 Output Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 関連する DC/DC 製品
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PWP PACKAGE
20-PINs
Top View
TPS54310 po_lvs412.gif

Pin Functions

PIN DESCRIPTION
NAME NO.
AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin. Make PowerPAD connection to AGND.
BOOT 5 Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver.
COMP 3 Error amplifier output. Connect compensation network from COMP to VSENSE.
PGND 11–13 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors.
PH 6–10 Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
PWRGD 4 Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or internal shutdown signal active.
RT 20 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA 18 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time.
SYNC 19 Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin.
VBIAS 17 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN 14–16 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
VSENSE 2 Error amplifier inverting input.