JAJSOP7A June   2011  – July 2022 TPS54325-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start and Pre-Biased Soft Start
      2. 7.3.2 Power Good
      3. 7.3.3 Output Discharge Control
      4. 7.3.4 Current Protection
      5. 7.3.5 Overvoltage and Undervoltage Protection
      6. 7.3.6 UVLO Protection
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Operation
      2. 7.4.2 PWM Frequency and Adaptive On-Time Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Bootstrap Capacitor Selection
        6. 8.2.2.6 VREG5 Capacitor Selection
        7. 8.2.2.7 Output Voltage Resistors Selection
      3. 8.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Information
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1 Soft Start and Pre-Biased Soft Start

The TPS54325-Q1 has an adjustable soft start. When the EN pin becomes high, 2.0-μA current begins charging the capacitor, which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start-up. Use the following equation to find the slow-start time. VFB voltage is 0.765 V and SS pin source current is 2 μA.

Equation 1. TSSms= C6nF× VREFISS (μA)= C6nF×0.7652

The TPS54325-Q1 contains a unique circuit to prevent current from being pulled from the output during start-up in the condition the output is prebiased. When the soft start commands a voltage higher than the prebias level (internal soft start becomes greater than feedback voltage (VFB)), the controller slowly activates synchronous rectification by starting the first low-side FET gate driver pulses with a narrow on time. The device then increments that on time on a cycle-by-cycle basis until it coincides with the time dictated by (1 – D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the prebias output, and ensures that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from prebiased start-up to normal mode operation.