JAJSGM5 December   2018 TPS54340B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と負荷電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation Output Current
      3. 8.3.3  Pulse Skip Eco-mode
      4. 8.3.4  Low Dropout Operation and Bootstrap Voltage (BOOT)
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Adjusting the Output Voltage
      7. 8.3.7  Enable and Adjusting Undervoltage Lockout
      8. 8.3.8  Internal Soft Start
      9. 8.3.9  Constant Switching Frequency and Timing Resistor (RT/CLK) pin)
      10. 8.3.10 Accurate Current Limit Operation and Maximum Switching Frequency
      11. 8.3.11 Synchronization to RT/CLK pin
      12. 8.3.12 Overvoltage Protection
      13. 8.3.13 Thermal Shutdown
      14. 8.3.14 Small Signal Model for Loop Response
      15. 8.3.15 Simple Small Signal Model for Peak-Current-Mode Control
      16. 8.3.16 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with VIN ≤ 4.5 V (Minimum VIN)
      2. 8.4.2 Operation with EN Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Buck Converter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1  Custom Design with WEBENCH® Tools
        2. 9.2.2.2  Selecting the Switching Frequency
        3. 9.2.2.3  Output Inductor Selection (LO)
        4. 9.2.2.4  Output Capacitor
        5. 9.2.2.5  Catch Diode
        6. 9.2.2.6  Input Capacitor
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Undervoltage Lockout Setpoint
        9. 9.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 9.2.2.10 Minimum VIN
        11. 9.2.2.11 Compensation
        12. 9.2.2.12 Discontinuous Conduction Mode and Eco-mode Boundary
        13. 9.2.2.13 Power Dissipation
      3. 9.2.3 Application Curves
    3. 9.3 Other Applications
      1. 9.3.1 Inverting Power
      2. 9.3.2 Split-Rail Power Supply
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Estimated Circuit Area
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.11 Compensation

There are several methods to design compensation for DC/DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope compensation is ignored, the actual crossover frequency is lower than the crossover frequency used in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater the modulator pole.

To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 44 and Equation 45. For COUT, use a derated value of 70 μF. Use equations Equation 46 and Equation 47 to estimate a starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 2411 Hz and ƒz(mod) is 455 kHz. Equation 45 is the geometric mean of the modulator pole and the ESR zero and Equation 47 is the mean of modulator pole and the switching frequency. Equation 46 yields 33.1 kHz and Equation 47 gives 26.9 kHz. Use the lower value of Equation 46 or Equation 47 for an initial crossover frequency. For this example, the target ƒco is 26.9 kHz.

Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole.

Equation 44. TPS54340B q_fpmod_lvsBK0.gif
Equation 45. TPS54340B q_fzmod_lvsBK0.gif
Equation 46. TPS54340B q_fco_48khz_lvsBK0.gif
Equation 47. TPS54340B q_fco_25khz_lvsBK0.gif

To determine the compensation resistor, R4, use Equation 48. Assume the power stage transconductance, gmps, is 12 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5 V, 0.8 V and 350 μA/V, respectively. R4 is calculated to be 11.6 kΩ and a standard value of 11.5 kΩ is selected. Use Equation 49 to set the compensation zero to the modulator pole frequency. Equation 49 yields 5740 pF for compensating capacitor C5. 5600 pF is used for this design.

Equation 48. TPS54340B q_R4_lvsBK0.gif
Equation 49. TPS54340B q_C5_lvsBK0.gif

A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value calculated from Equation 50 and Equation 51 for C8 to set the compensation pole. The selected value of C8 is 47 pF for this design example.

Equation 50. TPS54340B q_C8_lvsBK0.gif
Equation 51. TPS54340B q_C8_1overR4_slvsBK0.gif