JAJSGL2 December   2018 TPS543C20A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1  Soft-Start Operation
      2. 8.4.2  Input and VDD Undervoltage Lockout (UVLO) Protection
      3. 8.4.3  Power Good and Enable
      4. 8.4.4  Voltage Reference
      5. 8.4.5  Prebiased Output Start-up
      6. 8.4.6  Internal Ramp Generator
        1. 8.4.6.1 Ramp Selections
      7. 8.4.7  Switching Frequency
      8. 8.4.8  Clock Sync Point Selection
      9. 8.4.9  Synchronization and Stackable Configuration
      10. 8.4.10 Dual-Phase Stackable Configurations
        1. 8.4.10.1 Configuration 1: Master Sync Out Clock-to-Slave
        2. 8.4.10.2 Configuration 2: Master and Slave Sync to External System Clock
      11. 8.4.11 Operation Mode
      12. 8.4.12 API/Body Brake
      13. 8.4.13 Sense and Overcurrent Protection
        1. 8.4.13.1 Low-Side MOSFET Overcurrent Protection
        2. 8.4.13.2 High-Side MOSFET Overcurrent Protection
      14. 8.4.14 Output Overvoltage and Undervoltage Protection
      15. 8.4.15 Overtemperature Protection
      16. 8.4.16 RSP/RSN Remote Sense Function
      17. 8.4.17 Current Sharing
      18. 8.4.18 Loss of Synchronization
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: TPS543C20A Stand-alone Device
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Switching Frequency Selection
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Bootstrap Capacitor Selection
        6. 9.2.2.6 BP Pin
        7. 9.2.2.7 R-C Snubber and VIN Pin High-Frequency Bypass
        8. 9.2.2.8 Output Capacitor Selection
          1. 9.2.2.8.1 Response to a Load Transient
          2. 9.2.2.8.2 Ramp Selection Design to Ensure Stability
      3. 9.2.3 Application Curves
    3. 9.3 System Example
      1. 9.3.1 Two-Phase Stackable
        1. 9.3.1.1 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Package Size, Efficiency and Thermal Performance
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 WEBENCH®ツールによるカスタム設計
      2. 12.1.2 ドキュメントのサポート
        1. 12.1.2.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MOSFET RDS(ON)
RDS(on)HS HS FET VBST – VSW = 5 V, ID = 20 A, TJ = 25°C 3.4 mΩ
RDS(on)LS LS FET VDD = 5 V, ID = 20 A, TJ = 25°C 0.9 mΩ
tDEAD(LtoH) Power stage driver dead-time from Low-side off to High-side on(1) VDD ≥ 12 V, TJ = 25°C 12 ns
tDEAD(HtoL) Power stage driver dead-time from High-side off to Low-side on(1) VDDN ≥ 12 V, TJ = 25°C 15 ns
INPUT SUPPLY and CURRENT
VVIN Power stage voltage 4 16
VVDD VDD supply voltage 4 16
IVDD VDD bias current TA = 25°C, no load, power conversion enabled (no switching) 4.3 mA
IVDDSTBY VDD standby current TA = 25°C, no load, power conversion disabled 4.3 mA
UNDERVOLTAGE LOCKOUT
VVDD_UVLO VDD UVLO rising threshold 3.8 V
VVDD_UVLO_HYS VDD UVLO hysteresis 0.2 v
VVIN_UVLO VIN UVLO rising threshold 3.2 V
VVIN_UVLO_HYS VIN UVLO hysteresis 0.2 v
VEN_ON_TH EN on threshold 1.45 1.6 1.75 V
VHYS EN hysteresis 270 300 330 mV
IEN_LKG EN input leakage current –1 0 1 µA
INTERNAL REFERENCE VOLTAGE
VINTREF Internal REF voltage RVSEL = OPEN 1000 mV
VINTREFTOL Internal REF voltage tolerance TJ = –40°C to 125°C –0.5% 0.5%
VINTREF_VSEL Internal REF voltage range Programable by VSEL (pin 36) 0.6 1.1 V
OUTPUT VOLTAGE
IRSP RSP input current VRSP = 600 mV –1 1 µA
DIFFERENTIAL REMOTE SENSE AMPLIFIER
fUGBW Unity gain bandwidth(1) 5 8.5 MHz
A0 Open loop gain(1) 75 dB
SR SLew rate(1) ±10 V/µs
VICM Input common mode range(1) –0.2 1.7 V
VOFFSET Input offset voltage(1) VRSN-VGND = 0 mV –1 1 mV
VRSN-VGND = ±100 mV –1.9 1.9
SWITCHING FREQUENCY
FSW VO switching frequency maximum frequency for multi-phase is 1MHz VIN = 12 V, VVO = 1 V, RT = 66.5 kΩ 300 kHz
VIN = 12 V, VVO = 1 V, RT = 48.7 kΩ 400
VIN = 12 V, VVO = 1 V, RT = 39.2 kΩ 500
VIN = 12 V, VVO = 1 V, RT = 28.0 kΩ 700
VIN = 12 V, VVO = 1 V, RT = 22.6 kΩ 850
VIN = 12 V, VVO = 1 V, RT = 19.1 kΩ 1000
VIN = 12 V, VVO = 1 V, RT = 15.4 kΩ 1200
VIN = 12 V, VVO = 1 V, RT = 8.06 kΩ 2000
tON(min) Minimum on-time(1) DRVH rising to falling 30 ns
tOFF(min) Minimum off-time(1) DRVH falling to rising 250 ns
INTERNAL BOOTSTRAP SWITCH
VF Forward voltage VBP-VBST, TA = 25°C, IF = 5 mA 0.1 0.2 V
VSEL
VSEL Internal reference voltage RVSEL = 0 kΩ 0.6 V
RVSEL = 8.66 kΩ 0.7
RVSEL = 15.4 kΩ 0.75
RVSEL = 23.7 kΩ 0.8
RVSEL = 34.8 kΩ 0.85
RVSEL = 51.1 kΩ 0.9
RVSEL = 78.7 kΩ 0.95
RVSEL = OPEN 1
RVSEL = 121 kΩ 1.05
RVSEL = 187 kΩ 1.1
SOFT START
tSS Soft-start time VO rising from 0 V to 95% of final set point RSS = 0 kΩ 0.5 ms
RSS = 8.66 kΩ 1
RSS = 15.4 kΩ 2
RSS = Open 4
RSS = 23.7 kΩ 5
RSS = 34.8 kΩ 8
RSS = 51.1 kΩ 12
RSS = 78.7 kΩ 16
RSS = 121 kΩ 24
RSS = 187 kΩ 32
POWER ON DELAY
tPODLY Power-on delay time Delay from enable to switching 512 µs
PGOOD COMPARATOR
VPG(thresh) OV warning threshold on RSP pin, PGOOD fault threshold on rising VREF = 600 mV 108 112 116 %VREF
UV warning threshold on RSP pin, PGOOD fault threshold on falling VREF = 600 mV 84 88 92
VPGD(rise) PGOOD threshold on rising and UV warning threshold de-assertion threshold at RSP pin VREF = 600 mV 95 %VREF
VPGD(fall) PGOOD threshold on falling and OV warning threshold de-assertion threshold at RSP pin VREF = 600 mV 105 %VREF
RPGD PGOOD pulldown resistance IPGOOD = 5 mA, VRSP = 0 V 30 45 60 Ω
tPGDLY PGOOD delay time Delay for PGOOD going in 1.024 ms
Delay for PGOOD coming out 2 µs
VPGD(OL) PGOOD output low level voltage at no supply voltage VDD=0, IPGOOD = 80 µA 0.8 V
IPGLK PGOOD leakage current VPGOOD = 5 V 15 µA
CURRENT SHARE ACCURACY
ISHARE(acc) Output current sharing accuracy among stackable devices, defined as the ratio of the current difference between devices to total current(sensing error only)(1) IOUT ≥ 20 A/phase –15% 15%
IOUT ≤ 20 A/phase ±3 A
CURRENT DETECTION
VILIM VTRIP voltage range Rdson sensing 0.1 1.2 V
IOCP Low-side FET current protection threshold and tolerance RILIM= 33.2 kΩ 35 A
OC tolerance ±10%
IOCP Low-Side FET current protection threshold and tolerance RILIM= 23.7 kΩ 25 A
OC tolerance ±15%
IOCP_N Negative current limit threshold Valley-point current sense –23 A
ICLMP_LO Clamp current at VTRIP clamp at lowest 25°C, VTRIP = 0.1 V 5.5 6.5 7.5 A
HIGH-SIDE SHORT-CIRCUIT PROTECTION
IHSOC High-side short circuit protection fault threshold(1) 55 A
OV / UV PROTECTION
VOVP OVP threshold voltage OVP detect voltage 113 117 121 %VREF
tOVPDLY OVP response time(1) OVP response time with 100-mV overdrive 1 µs
VUVP UVP threshold voltage UVP detect voltage 79 83 87 %VREF
tUVPDLY UVP delay(1) UVP delay 1.5 µs
tHICDLY Hiccup delay time Regular tSS setting 7 × tSS ms
BP LDO REGULATOR
BP LDO output voltage VIN = 12 V, ILOAD = 0 to 10 mA 4.5 5 5.5 V
VBPUVLO BP UVLO threshold voltage Wakeup 3.32 V
Shutdown 3.11
VLDOBP LDO low dropout voltage VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C 365 mV
ILDOMAX LDO overcurrent limit VIN = 12 V, TA = 25°C 100 mA
SYNCHRONIZATION
VIH(SYNC) High-level input voltage 2 V
VIL(SYNC) Low-level input voltage 0.8
tPSW(SYNC) Sync input minimum pulse width 100 ns
FSYNC Synchronization frequency 300 2000 kHz
Dual-phase 300 1000
tSYNC to SW Sync to SW delay tolerance, percentage from phase-to-phase(1) FSYNC = 300 kHz to 1 MHz, 10%
tLose_SYNC_delay Delay when lose sync clock(1) FSYNC = 300 kHz 5 µs
THERMAL SHUTDOWN
TSDN Built-in thermal shutdown threshold(1) Shutdown temperature 155 165 °C
Hysteresis 30
(1) Specified by design. Not production tested.