JAJSGL2 December   2018 TPS543C20A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1  Soft-Start Operation
      2. 8.4.2  Input and VDD Undervoltage Lockout (UVLO) Protection
      3. 8.4.3  Power Good and Enable
      4. 8.4.4  Voltage Reference
      5. 8.4.5  Prebiased Output Start-up
      6. 8.4.6  Internal Ramp Generator
        1. 8.4.6.1 Ramp Selections
      7. 8.4.7  Switching Frequency
      8. 8.4.8  Clock Sync Point Selection
      9. 8.4.9  Synchronization and Stackable Configuration
      10. 8.4.10 Dual-Phase Stackable Configurations
        1. 8.4.10.1 Configuration 1: Master Sync Out Clock-to-Slave
        2. 8.4.10.2 Configuration 2: Master and Slave Sync to External System Clock
      11. 8.4.11 Operation Mode
      12. 8.4.12 API/Body Brake
      13. 8.4.13 Sense and Overcurrent Protection
        1. 8.4.13.1 Low-Side MOSFET Overcurrent Protection
        2. 8.4.13.2 High-Side MOSFET Overcurrent Protection
      14. 8.4.14 Output Overvoltage and Undervoltage Protection
      15. 8.4.15 Overtemperature Protection
      16. 8.4.16 RSP/RSN Remote Sense Function
      17. 8.4.17 Current Sharing
      18. 8.4.18 Loss of Synchronization
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: TPS543C20A Stand-alone Device
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Switching Frequency Selection
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Input Capacitor Selection
        5. 9.2.2.5 Bootstrap Capacitor Selection
        6. 9.2.2.6 BP Pin
        7. 9.2.2.7 R-C Snubber and VIN Pin High-Frequency Bypass
        8. 9.2.2.8 Output Capacitor Selection
          1. 9.2.2.8.1 Response to a Load Transient
          2. 9.2.2.8.2 Ramp Selection Design to Ensure Stability
      3. 9.2.3 Application Curves
    3. 9.3 System Example
      1. 9.3.1 Two-Phase Stackable
        1. 9.3.1.1 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Package Size, Efficiency and Thermal Performance
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 WEBENCH®ツールによるカスタム設計
      2. 12.1.2 ドキュメントのサポート
        1. 12.1.2.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.13.1 Low-Side MOSFET Overcurrent Protection

The utilizes ILIM pin to set the OCP level. The ILIM pin must be connected to AGND through the ILIM voltage setting resistor, RILIM. The ILIM terminal sources IILIM current, which is around 11.2 μA typically at room temperature, and the ILIM level is set to the OCP ILIM voltage VILIM as shown in Equation 2. In order to provide both good accuracy and cost effective solution, supports temperature compensated MOSFET RDS(on) sensing.

Equation 2. TPS543C20A sluscd4_equation2.gif
Consider RDS(on) variation vs VDD in calculation

Also, performs both positive and fixed negative inductor current limiting.

The inductor current is monitored by the voltage between GND pin and SW pin during the OFF time. ILIM has 1200 ppm/°C temperature slope to compensate the temperature dependency of the RDS(on). The GND pin is used as the positive current sensing node.

The device has cycle-by-cycle over-current limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the period that the inductor current is larger than the overcurrent ILIM level. VILIM sets the peak level of the inductor current. Thus, the load current at the overcurrent threshold, IOCP, can be calculated as shown in .

Equation 3. TPS543C20A Eq_Iocp_SLUSCD4.gif

where

  • RDS(on) is the on-resistance of the low-side MOSFET.

Equation 3 is valid for VDD ≥ 5 V. Use 0.58 mΩ for RDS(on) in calculation, which is the pure on-resistance for current sense.

If an overcurrent event is detected in a given switching cycle, the device increments an overcurrent counter. When the device detects three consecutive overcurrent (either high-side or low-side) events, the converter responds, entering continuous restart hiccup. In continuous hiccup mode, the device implements a 7 soft-start cycle timeout, followed by a normal soft-start attempt. When the overcurrent fault clears, normal operation resumes; otherwise, the device detects overcurrent and the process repeats.