JAJS383E September   2009  – April 2018 TPS54418

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation and Output Current
      3. 8.3.3  Bootstrap Voltage (Boot) and Low Dropout Operation
      4. 8.3.4  Error Amplifier
      5. 8.3.5  Voltage Reference
      6. 8.3.6  Adjusting the Output Voltage
      7. 8.3.7  Enable and Adjusting Undervoltage Lockout
      8. 8.3.8  Soft-Start Pin
      9. 8.3.9  Sequencing
      10. 8.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      11. 8.3.11 Overcurrent Protection
      12. 8.3.12 Frequency Shift
      13. 8.3.13 Reverse Overcurrent Protection
      14. 8.3.14 Synchronize Using the RT/CLK Pin
      15. 8.3.15 Power Good (PWRGD Pin)
      16. 8.3.16 Overvoltage Transient Protection
      17. 8.3.17 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Small Signal Model for Loop Response
      2. 8.4.2 Simple Small Signal Model for Peak Current Mode Control
      3. 8.4.3 Small Signal Model for Frequency Compensation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Step One: Select the Switching Frequency
        2. 9.2.2.2  Step Two: Select the Output Inductor
        3. 9.2.2.3  Step Three: Choose the Output Capacitor
        4. 9.2.2.4  Step Four: Select the Input Capacitor
        5. 9.2.2.5  Step Five: Minimum Load DC COMP Voltage
        6. 9.2.2.6  Step Six: Choose the Soft-Start Capacitor
        7. 9.2.2.7  Step Seven: Select the Bootstrap Capacitor
        8. 9.2.2.8  Step Eight: Undervoltage Lockout Threshold
        9. 9.2.2.9  Step Nine: Select Output Voltage and Feedback Resistors
          1. 9.2.2.9.1 Output Voltage Limitations
        10. 9.2.2.10 Step 10: Select Loop Compensation Components
        11. 9.2.2.11 Power Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 WEBENCH®ツールによるカスタム設計
      2. 12.1.2 開発サポート
    2. 12.2 商標
    3. 12.3 静電気放電に関する注意事項
    4. 12.4 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

–40°C ≤ TJ ≤ 150°C, 2.95 ≤ VVIN ≤ 6 V (unless otherwise noted) over operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN)
VVIN Operating input voltage 2.95 6 V
VUVLO Internal under voltage lockout threshold No voltage hysteresis, rising and falling 2.6 2.8 V
IQ(vin) Shutdown supply current VEN = 0 V, TA = 25°C, 2.95 V ≤ VVIN ≤ 6 V 2 5 μA
Iq Quiescent current VVSENSE = 0.9 V, VVIN = 5 V, 25°C,
RT = 400 kΩ		 350 500 μA
ENABLE AND UVLO (EN)
VTH(en) Enable threshold Rising 1.16 1.25 1.37 V
Falling 1.18
IEN Input current Enable rising threshold + 50 mV –3.2 μA
Enable falling threshold – 50 mV –0.65
VOLTAGE REFERENCE (VSENSE)
VREF Voltage reference 2.95 V ≤ VVIN ≤ 6 V, –40°C <TJ< 150°C 0.795 0.803 0.811 V
MOSFET
RDS(HFET) High-side switch resistance (VBOOT – VPH) = 5 V 30 60 mΩ
(VBOOT – VPH) = 2.95 V 44 70
RDS(LFET) Low-side switch resistance VVIN = 5 V 30 60 mΩ
VVIN = 2.95 V 44 70
ERROR AMPLIFIER
IIN Input current 7 nA
gM(ea) Error amplifier transconductance –2 μA < ICOMP< 2 μA, VCOMP = 1 V 225 μS
gm(EA,ss) Error amplifier transconductance during soft-start –2 μA < ICOMP< 2 μA, VCOMP = 1 V,
VVSENSE = 0.4 V		 70 μS
ICOMP Error amplifier source/sink VCOMP = 1 V, 100 mV overdrive ±20 μA
gM COMP to ISWITCH transconductance 13 A/V
CURRENT LIMIT
ILIM Current limit threshold Instantaneous peak current 5.0 6.4 A
THERMAL SHUTDOWN
TSD Thermal Shutdown 175 °C
TSD(hyst) Hysteresis 15 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK)
fSW Switching frequency range using RT mode 200 2000 kHz
fSW Switching frequency RRT = 400 kΩ 400 500 600 kHz
fSW Switching frequency range using CLK mode 300 2000 kHz
tMIN(CLK) Minimum CLK pulse width 75 ns
VRT/CLK RT/CLK voltage RRT/CLK = 400 kΩ 0.5 V
VIH(CLK) RT/CLK high threshold 1.6 2.2 V
VIL(CLK) RT/CLK low threshold 0.4 0.6 V
tDLY RT/CLK falling edge to PH rising edge delay fSW = 500 kHz with RRT resistor in series 90 ns
tLOCK(PLL) PLL lock-in time fSW = 500 kHz 14 μs
HIGH-SIDE POWER MOSFET (PH)
tON(min) Minimum on time Measured at 50% points on PH, IOUT = 4 60 ns
Measured at 50% points on PH, VVIN = 5 V,
IOUT = 0 A		 110
tOFF(min) Minimum off time Prior to skipping off pulses,
(VBOOT – VPH) = 2.95 V, IOUT = 4		 60 ns
tRISE Rise time VVIN = 5 V 1.5 V/ns
tFALL Fall time VVIN = 5 V 1.5 V/ns
BOOT (BOOT)
RBOOT BOOT charge resistance VVIN = 5 V 16 Ω
VUVLO(Boot) BOOT-PH UVLO VVIN = 2.95 V 2.1 V
SOFT-START (SS )
ICHG Charge current VSS = 0.4 V 1.8 μA
VSSxREF SS to reference crossover 98% nominal 0.9 V
VDSCHG(SS) SS discharge voltage (overload) VVSENSE = 0 V 20 μA
IDSCHG(SS) SS discharge current (UVLO, EN, thermal fault) VVIN = 5 V, VSS = 0.5 V 1.25 mA
POWER GOOD (PWRGD)
VTH(PG) VSENSE threshold VVSENSE falling (fault) 91% VREF
VVSENSE rising (good) 93%
VVSENSE rising (fault) 107%
VVSENSE falling (Good) 105%
VHYST(PG) Hysteresis VVSENSE falling 2%
IPH(lkg) Output high leakage VVSENSE = VREF, VPWRGD = 5.5 V 2 nA
RPG Power Good on-resistance 100 Ω
VOL Low-level output voltage IPWRGD = 3.5 mA 0.3 V
VMIN(PG) Minimum input voltage for valid output VPWRGD< 0.5 V , IOUT = 100 μA 1.2 1.6 V