JAJSBF8B June 2011 – April 2018 TPS54478
PRODUCTION DATA.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 5 | — | Analog Ground should be electrically connected to GND close to the device. |
BOOT | 13 | O | A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed. |
COMP | 7 | I/O | Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. |
EN | 15 | I | Enable pin, internal pull-up current source. Pull below 1.21 V to disable. Float to enable. Can be used to set the on/off threshold (adjust UVLO) with two additional resistors. |
GND | 3, 4 | — | Power Ground. This pin should be electrically connected directly to the power pad under the IC. |
PH | 10, 11, 12 | O | The source of the internal high side power MOSFET, and drain of the internal low side (synchronous) rectifier MOSFET. |
PWRGD | 14 | O | An open drain output; asserts low if output voltage is low due to thermal shutdown, overcurrent, over/under-voltage or EN shut down. |
RT/CLK | 8 | I | Resistor Timing or External Clock input pin. |
SS/TR | 9 | I | Slow start and tracking. An external capacitor connected to this pin sets the output voltage rise time. The SS provides higer charge current when SS is below 0.15V, resulting in two slopes of the SS voltage.
This pin can also be used for tracking. |
Thermal Pad | 17 | — | GND pin should be connected to the exposed thermal pad for proper operation. This thermal pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance. |
VIN | 1, 2, 16 | I | Input supply voltage, 2.95 V to 6 V. |
VSENSE | 6 | I | Inverting node of the transconductance (gm) error amplifier. |